Intel 80386 User Manual

TABLE OF CONTENTS
. Page
3.5 Bus Lock ... ...... ... ...... ........ ..... ... ... ... ....... .... .... .... ......... ... ...................... .... ...... 3-32
3.5.1 Locked
Cycle Activators ..... ... ... ....... ....... .... .... ......... ....... .................. ... ....... 3-32
3.5.2 Locked
Cycle Timing .......... ... ... ... ....... .... .... .... ......... ...... .......... ......... ... .... ... 3-32
3.5.3
LOCK# Signal Duration ...... ...... ... ... ..... ....... ....... ...... ...... ... ..... ... ... ..... ......... 3-33
3.6 HOLD/HLDA
(Hold Acknowledge) ................................................................. 3-34
3.6.1 HOLD/HLDA
Timing ................................................................................... 3-34
3.6.2
HOLD Signal Latency............. ... ...... ....... ..... ............ ......... ... ............. .... ...... 3-36
3.6.3
HOLD State Pin Conditions ........................................................................ 3-36
3.7 Reset ............................................................................................................. 3-37
3.7.1
RESET Timing ....... :.................................................................................... 3-37
3.7.2
80386 Internal States ................................................................................. 3-38
3.7.3
80386 External States ............................................................................... 3-38
CHAPTER 4
PERFORMANCE
CONSIDERATIONS
4.1 Wait States and Pipelining .... .............. ..... .... ... ....... ...... ...... ... ........ ........ .... ..... 4-1
CHAPTER 5
COPROCESSOR HARDWARE INTERFACE
5.1 80287 Numeric Coprocessor Interface . ....... ....... .......... ........ ........ .... .... ..... .... 5-2
5.1.1
80287 Connections .................................................................................... 5-2
5.1.2
80287 Bus Cycles ...................................................................................... 5-2
5.1.3
80287 Clock Input ...................................................................................... 5-4
5.2
80387 Numeric Coprocessor Interface .......................................................... 5-4
5.2.1
80387 Connections .................................................................................... 5-4
5.2.2
80387 Bus Cycles ...................................................................................... 5-6
5.2.3
80387 Clock Input ...................................................................................... 5-6
5.3
Local Bus Activity with the 80287/80387 ...................................................... 5-7
5.4
Designing an Upgradable 80386 System ...................................................... 5-8
5.4.1
80287/80387 Recognition .......................................................................... 5-8
5.4.1.1 Hardware Recognition
.of the NPX .......................................................... 5-8
5.4.1.2 Software Recognition of the NPX ............................................................ 5-8
5.4.2
80387 Emulator .......................................................................................... 5-10
CHAPTER 6
MEMORY
INTERFACING
6.1 Memory Speed versus Performance and Cost ... ........ ........ ...... ..... ... ... ....... ... 6-1
6.2 Basic Memory Interface ........... ... ........ .... .... ... .......... ... ... ..... ... ........ ... .... ...... ... 6-1
6.2.1 PAL Devices ............................................................................................... 6-2
6.2.2 Address
Latch . ... ........ ... ...... ........ ... ........... ... ............ ........ ... ... ... ... ... ..... ...... 6-3
6.2.3 Address Decoder
.. .................... ......... ........ ... ...... ... ........ ..... ...... .... ..... ........ 6-4
6.2.4 Data Transceiver
... ................. ..... ... ....... ....... ......... ... ... ..... ...... ...... .... .... ...... 6-5
6.2.5
Bus Control Logic .......... .................. ..... ....... ...... ..... ........ ... ... ... ........ .......... 6-6
vi

Intel 80386 Specifications

General

Clock Speed	12 MHz to 40 MHz
Transistor Count	275, 000
Addressable Memory	4 GB
Data Bus Width	32-bit
Instruction Set	x86
Introduction Date	October 17, 1985
Virtual Memory	Yes
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Manufacturer	Intel
Model	80386
Address Bus Width	32-bit
Voltage	5V
Manufacturing Process	1.5 µm
Cache	No on-chip cache
FPU	Optional (80387)
Bus Interface	32-bit
Process Technology	CHMOS III
Package	PGA