Intel 80386 User Manual

TABLE OF CONTENTS
Page
8.2.2 8-Bit I/O .. ... ...... .... ..... ... ....... ....... ..... ... ... ... ....... ........ .... ........... ... ....... .......... 8-2
8.2.3 16-Bit I/O ........................................................................................... '" ..... 8-4
8.2.4 32-Bit I/O ... ... ... .... ..... ..... .......... ...... ....... ....... .... ........... ......... ....... .... ..... ...... 8-4
8.2.5 Linear Chip Selects .................................... '" .............. ........ ... ... ... .............. 8-4
8.3 Basic I/O Interface ........................................................ :................................ 8-4
8.3.1 Address Latch ....... ................... ... ... .... ... .... ... .... .... ...... .... ........ ......... ..... ...... 8-5
8.3.2 Address Decoder .... ............. ......
... ..... ............ ....... ..... ......... ... ........ ...... ...... 8-6
8.3.3 Data Transceiver ........................................................ , ... ........ ......... ........... 8-8
8.3.4 Bus Control Logic ..... ..... ....... ......... .... ....... .............. ....... ... ..... ...... ..... ......... 8-8
8.4 Timing Analysis for I/O Operations ................................................................ 8-9
8.5 Basic
I/O Examples ........... '" ........ ...... ....... ....... .... .... ...... ........... .... ....... ......... 8-14
8.5.1 8274 Serial Controller .............................................................................. '" 8-14
8.5.2 82380 Programmable Interrupt Controller .. ........ ...... .............. .......... .......... 8-15
8.5.2.1 Cascaded Interrupt Controllers to the 82380 PIC .... ...... ........ ................. 8-15
8.5.3 8259A
Interrupt Controller .............. .............. ............ ...... .......... ........ .......... 8-15
8.5.3.1
Single Interrupt Controller .... ........ .................................. .......... ...... ......... 8-16
8.5.3.2 Cascaded Interrupt Controllers ...................................................... ,.. ...... 8-16
8.5.3.3
Handling More Than 64 Interrupts ...... .............................. ................ ....... 8-17
8.6 80286-Compatible Bus Cycles .................................... ;................................. 8-17
8.6.1 AO/A 1 Generator ...................... , ..................................................... ,........... 8-18
8.6.2 SO#/S1# Generator .................................................................................. 8-18
8.6.3 Wait-State Generator ........ ...... ........ ...... ................ ...... .............. ........ ......... 8-19
8.6.4 Bus
Controller and Bus Arbiter .... ................ .......... ........ ................ ............ 8-20
8.6.5 82380 Integrated System Peripheral........ .............. ............ ................. ........ 8-21
8.6.6 82258 ADMA Controller ........................ ........ .............. ................ ........ ....... 8-23
8.6.6.1 82258 as Bus Master .... .............. .......... .................. ........................ ........ 8-25
8.6.6.2 82258 as
Peripheral .................................... :........................................... 8-26
8.6.7 82586 LAN Coprocessor ............................................................................ 8-27
8.6.7.1 Dedicated
CPU ........................................................................................ 8-28·
8.6.7.2 Decoupled Dual-Port Memory ................................................................. 8-29
8.6.7.3 Coupled Dual-Port Memory ..................................................................... 8-30
8.6.7.4 Shared Bus ............................................................................................. 8-30
CHAPTER 9
MUL
TIBUS® I AND 80386
9.1 MUL TIBUS® I (IEEE 796) .... ...................... ............ .......... .......................... ..... 9-1
9.2 MUL TIBUS® I Interface Example .... .......... ................ ........ .......... .......... ......... 9-2
9.2.1 Address Latches and Data Transceivers ........ .......... ...... ........ ...... ........ ...... 9-2
9.2.2 Address Decoder .. ....... ............. ................... ......... ............... ........ ........ ...... 9-5
9.2.3 Wait-State Generator ................................................................................. 9-5
9.2.4 Bus Controller and Bus Arbiter .................................................................. 9-7
9.3 Timing Analysis of MUL TIBUS® I Interface ................ .............. ............ .......... 9-10
9.4 82289 Bus Arbiter .............. .......... ........ .............. .......... ...... ...... .......... ........... 9-10
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Intel 80386 Specifications

General

Clock Speed	12 MHz to 40 MHz
Transistor Count	275, 000
Addressable Memory	4 GB
Data Bus Width	32-bit
Instruction Set	x86
Introduction Date	October 17, 1985
Virtual Memory	Yes
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Manufacturer	Intel
Model	80386
Address Bus Width	32-bit
Voltage	5V
Manufacturing Process	1.5 µm
Cache	No on-chip cache
FPU	Optional (80387)
Bus Interface	32-bit
Process Technology	CHMOS III
Package	PGA