Intel 80386 User Manual

TABLE OF CONTENTS
9.4.1 Priority Resolution ..................................................................................... .
9.4.2 82289 Operating Modes ........................................................................... .
Q.4.3 MUL TIBUS® I Locked Cycles .................................................................... .
9.5 Other
MULTIBUS® I Design Considerations ................................................. .
9.5.1
Interrupt-Acknowledge on MUL TIBUS® I .................................................. ..
9.5.2 Byte Swapping during MUL TIBUS® I Byte Transfers ................................ .
9.5.3 Bus Timeout Function for MUL
TIBUS® I Accesses ................................... .
9.5.4 MUL
TIBUS® I Power Failure Handling ....................................................... .
9.6
iL~XTM Bus Expansion .................................................................................. .
9.7
Dual-Port RAM with MULTIBUS® I ............................................................... .
9.7.1
AVOiding Deadlock with Dual-Port RAM
CHAPTER 10
MUL TIBUS® II AND 80386
10.1 MUL TIBUS® II Standard
10.2
Parallel System Bus (iPSB) ........................................................ : ................ .
10.2.1
iPSB Interface ......................................................................................... .
10.2.1.1 BAC
Signals ......................................................................................... .
10.2.1.2
MIC Signals .......................................................................................... .
10.3
Local Bus Extension (iLBXTM II) ................................................................... .
10.4
Serial System Bus (iSSB) ........................................................................... .
CHAPTER 11
PHYSICAL DESIGN AND DEBUGGING
Page
9-11
9-11
9-14
9-14
9-14
9-16
9-17
9-17
9-18
9-19
9-20
10-1
10-1
10-2
10-4
10-6
10-7
10-7
11.1 Power and Ground Requirements ............................................................... 11-1
11 .1.1 Power and Ground Planes ....................................................................... 11-1
11 .1.2 Decoupling Capacitors ............................................................................. 11-2
11.2 High-Frequency Design Considerations .... ... .... ... ..... ..... ... ........ ......... .......... 11-3
11.2.1 Line Termination ....................................................................................... 11-4
11.2.2
Interference ... ......... ....... ...... .......... ..... ...... ...... .... .... ..... ... ... ... ......... ....... .... 11-5
11.2.3 Latchup .................................................................................................... 11-7
11.3
Clock Distribution and Termination ............................................................. 11-7
11.4
Thermal Characteristics ............................................................................... 11-7
11.5 Debugging Considerations .......................................................................... 11-10
11.5.1 Hardware Debugging Features ................................................................ 11-10
11.5.2 Bus
Interface ................................................................................. ; .......... 11-11
11 .5.3 Simplest Diagnostic Program .. ... ... ... ....... ... ... ....... ......... ...... ........ ...... ....... 11-11
11 .5.4 Building and Debugging a System Incrementally .. ......... ... ... ........ ... ... ....... 11-12
11.5.5 Other
Simple Diagnostic Software ........................................................... 11-14
11.5.6 Debugging Hints ....................................................................................... 11-14
ix

Intel 80386 Specifications

General

Clock Speed	12 MHz to 40 MHz
Transistor Count	275, 000
Addressable Memory	4 GB
Data Bus Width	32-bit
Instruction Set	x86
Introduction Date	October 17, 1985
Virtual Memory	Yes
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Manufacturer	Intel
Model	80386
Address Bus Width	32-bit
Voltage	5V
Manufacturing Process	1.5 µm
Cache	No on-chip cache
FPU	Optional (80387)
Bus Interface	32-bit
Process Technology	CHMOS III
Package	PGA