Intel 80386

TABLE OF CONTENTS
CHAPTER 12
TEST CAPABILITIES
12.1 Internal Tests .............................................................................................. 12-1
12.1.1 Automatic Self-Test .................................................................................. 12-1
12.1.2 Translation Lookaside Buffer Tests .......................................................... 12-2
12.2
Board-Level Tests ....................................................................................... 12-5
APPENDIX A
LOCAL !:IUS CONTROL PAL DESCRIPTIONS
PAL-1 Functions ............... .............. ............................................................ .......... A-1
PAL-2 Functions ................................................................................................... A-2
PAL Equations ........................ ............................................................................. A-2
APPENDIX B
80387 EMULATOR PAL DESCRIPTION
APPENDIX
C
DRAM
PAL DESCRIPTIONS
DRAM State PAL ................................................................................................ .
DRAM Control PAL ............................................................................................. .
Refresh
Interval Counter PAL .............................................................................. .
Refresh Address Counter
PAL ............................................................................ .
Timing Parameters
Figures
C-1
C-13
C-13
C-13
C-25
Figure Title Page
1-1 80386 System Block Diagram ................................................................ 1-2
2-1 Instruction Pipelining ............................................................................... 2-1
2-2 80386 Functional Units ........................................................................... 2-2
3-1 CLK2 and CLK Relationship ................................................................... 3-5
3-2
80386 Bus States Timing Example ...................................... .................. 3-6
3-3 Bus
State Diagram (Does Not Include Address Pipelining) ..................... 3-7
3-4
Non-Pipelined Address and Pipelined Address Differences .................... 3-8
3-5 Consecutive Bytes
in Hardware Implementation ...................... .............. 3-9
3-6 Address, Data Bus, and Byte Enables for 32-Bit Bus ............................ 3-9
3-7 Misaligned Transfer .............. .................................................................. 3-11
3-8 Non-Pipelined Address Read Cycles ...................................................... 3-12
3-9
Non-Pipelined Address Write Cycles ...................................................... 3-15
3-10 Pipelined Address Cycles ....................................................................... 3-16
3-11 Interrupt Acknowledge Bus Cycles ......................................................... 3-18
3-12
Internal NA# and BS16# Logic ............................................................. 3-20
3-13 32-Bit and 16-Bit Bus Cycle Timing ........................................................ 3-21
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