Intel 80386 User Manual

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TABLE OF CONTENTS
Title
32-Bit and 16-Bit Data Addressing ........................................................ .
Connecting 82384 to 80386 .................................................................. .
Using CLK to Determine Bus Cycle Start .............................................. .
Clock Generator .................................................................................... .
ADS#
Synchronizer .............................................................................. .
Error Condition Caused by Unlocked Cycles ......................................... .
LOCK# Signal during Address Pipelining ............................................. ..
Bus State Diagram with HOLD State ................................................... ..
Typical RC RESET Timing Circuit .......................................................... .
RESET, CLK, and CLK2 Timing ............................................................ .
80386 System with 80287 Coprocessor ............................................... .
80386 System with 80387 Coprocessor .............................................. ..
Pseudo-Synchronous Interface .............................................................. .
Software Routine to Recognize the 80287 ............................................ .
80387 Emulator Schematic ................................................................... .
Basic Memory Interface Block Diagram ................................................. .
PAL Equation and Implementation ....................................................... ..
PAL Naming Conventions ...................................................................... .
Bus Control Logic .................................................................................. .
Bus Control Signal Timing ..................................................................... .
150-Nanosecond EPROM Timing Diagram ............................................ .
100-Nanosecond SRAM Timing Diagram .............................................. .
3-CLK DRAM Controller Schematic ...................................................... ..
3-CLK DRAM Controller Cycles ............................................................ ..
2-CLK DRAM Controller Schematic ...................................................... ..
2-CLK DRAM Controller Cycles ............................................................. .
Refresh Request Generation ................................................................. .
Cache Memory System ......................................................................... .
Fully Associative Cache Organization .................................................... .
Direct Mapped Cache Organization ....................................................... .
Two-Way Set Associative Cache Organization ..................................... .
Stale Data Problem ................................................................................ .
Bus Watching ........................................................................................ .
Hardware Transparency ........................................................................ .
Non-Cacheable Memory ........................................................................ .
Example of Cache Memory Organization .............................................. .
32-Bit to 8-Bit Bus Conversion .............................................................. .
Linear Chip Selects ................................................................................ .
Basic I/O Interface Block Diagram ......................................................... .
Basic I/O Interface Circuit ...................................................................... .
Basic I/O Timing Diagram ...................................................................... .
8274
Interface ....................................................................................... .
Single 8259A Interface .......................................................................... .
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Intel 80386 Specifications

General

Clock Speed	12 MHz to 40 MHz
Transistor Count	275, 000
Addressable Memory	4 GB
Data Bus Width	32-bit
Instruction Set	x86
Introduction Date	October 17, 1985
Virtual Memory	Yes
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Manufacturer	Intel
Model	80386
Address Bus Width	32-bit
Voltage	5V
Manufacturing Process	1.5 µm
Cache	No on-chip cache
FPU	Optional (80387)
Bus Interface	32-bit
Process Technology	CHMOS III
Package	PGA