Intel 80386 User Manual

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TABLE OF CONTENTS
Title
80286-Compatible Interface .................................................................. .
AO, A1, and BHE# Logic ...................................................................... ..
SO#/S1 # Generator Logic .................................................................... .
Wait-State Generator Logic ................................................................... .
82288 and 82289 Connections ............................................................ ..
80386/82380 Interface .......................................................................... .
HOLD and HLDA Logic for 80386-82258 Interface .............................. ..
82258 Slave Mode Interface .................................................................. .
LAN Station ........................................................................................... .
Decoupled Dual-Port Memory Interface ................................................ ..
Coupled Dual-Port Memory Interface .................................................... .
Shared Bus Interface ............................................................................. .
80386-MUL TIBUS® I Interface .............................................................. .
MUL TIBUS® I Address Latches and Data Transceivers ........................ .
Wait-State Generator Logic ........................ , ......................................... ..
MUL TIBUS® Arbiter and Bus Controller ................................................ .
MUL TIBUS® I Read Cycle Timing ........................................................ ..
MUL TIBUS® I Write Cycle Timing ........................................................ ..
Bus Priority Resolution .......................................................................... .
Operating Mode Configurations ............................................................. .
. Bus-Select Logic for Interrupt Acknowledge ........................................ ..
Byte-Swapping Logic ............................................................................. .
Bus-Timeout Protection Circuit .............................................................. .
iLBX'" Signal Generation ....................................................................... .
iPSB Bus Cycle Timing .......................................................................... .
iPSB Bus Interface ................................................................................ .
Reducing Characteristic Impedance ...................................................... .
Circuit without Decoupling .................................................................... ;.
Decoupling Chip Capacitors ................................................................. ..
Decoupling Leaded Capacitors .............................................................. .
Series Termination ................................................................................. .
Split Termination .......... : .............................................................. ~ .......... .
Avoid Closed-Loop Signal Paths .......................................................... ..
CLK2 Series Termination ...................................................................... ..
CLK2 Loading ....................................................................................... ..
CLK2 Waveforms .................................................................................. .
4-Byte Diagnostic Program .................................................................... .
More Complex Diagnostic Program ...................................................... ..
Object Code for Diagnostic Program .............................................. , ..... ..
80386 Self-Test ..................................................................................... .
TLB Test Registers ............................................................................... .
PAL-1 State Listings .............................................................................. .
PAL-2 State Listings .............................................................................. .
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Intel 80386 Specifications

General

Clock Speed	12 MHz to 40 MHz
Transistor Count	275, 000
Addressable Memory	4 GB
Data Bus Width	32-bit
Instruction Set	x86
Introduction Date	October 17, 1985
Virtual Memory	Yes
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Manufacturer	Intel
Model	80386
Address Bus Width	32-bit
Voltage	5V
Manufacturing Process	1.5 µm
Cache	No on-chip cache
FPU	Optional (80387)
Bus Interface	32-bit
Process Technology	CHMOS III
Package	PGA