MEMORY INTERFACING
• For a single DRAM bank rather than two, the user should tie the DRAM State PAL A2
input
low,
leave RAS1# unconnected (only RASO#
is
used), and feed the 80386 address
bit A2 into the address multiplexer. The DRAM State PAL equations can be modified
to change the
RASl#
output to duplicate the RASO# output for more drive capability,
and the A2 input can
be
used as another chip-select input. When only
one
bank
is
used,
no
accesses can
be
interleaved, and back-to-back accesses run with one wait state with
the 2-CLK design and three wait states with the 3-CLK design (independent of address
pi
pelining).
6.3.5
Refresh Cycles
All DRAMs require periodic refreshing of their data. For most DRAMs, periodic activation
of each
of
the row address signals internally refreshes the data
in
every column of the
row.
Almost all DRAMs allow a RAS-only refresh cycle, the timing of which
is
the same
as
a
read cycle, except that only the RAS signals are activated (no CAS signals), and all of the
data pins are
in
the high impedance state.
Both the 3-CLK and 2-CLK designs
use
RAS-only refresh. The address multiplexer
is
placed
in
the high impedance state, and the Refresh Address Counter PAL
is
enabled to output the
address
of
the next row to
be
refreshed. Then the DRAM State PAL activates both RASO#
and RAS 1 # to refresh the selected row for both banks at once. After the refresh cycle
is
complete, the Refresh Address Counter PAL increments
so
that the next refresh cycle
refreshes the next sequential
row.
The frequency of refreshing and the number of
rows
to be refreshed depend
on
the type of
DRAM. For most larger DRAMs (64KxN and larger), only the lower eight multiplexed
address bits (A
7-AO,
256 rows) must be supplied for the refresh cycle; the upper address
bits are ignored. The Refresh Address Counter PAL must output only eight bits and only
the lower eight bits of the address multiplexer must be placed
in
the high impedance state.
The OE# signals of the higher order address multiplexers can be tied
low.
Larger DRAMs
generally require refresh every 4 milliseconds. The following sections describe refresh specif-
ically for larger DRAMs, although the concepts apply to smaller DRAMs.
6.3.5.1
DISTRIBUTED
REFRESH
In distributed refresh, the 256 refresh cycles are distributed equally within the 4-millisecond
interval. Every 15.625 microseconds (4 milliseconds/256), a single row refresh
is
performed.
After 4 milliseconds all 256 rows have been refreshed, and the pattern repeats. Both the
3-CLK and 2-CLK designs use distributed refresh.
The Refresh Interval Counter
PAL
is
programmed to request a single distributed refresh
cycle
at
intervals slightly under 15.625 microseconds. The counter requests a new refresh
cycle after a preset number of CLK cycles. This number
is
dependent
on
the CLK frequency
and can be calculated
as
follows for a 16-MHz CLK signal:
16
MHz
x 15.625 microseconds -
4/256
= 249.98
=
249
CLK cycles
6-25
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