Intel 80386

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I
DRAM READ BANK 0
DRAM READ BANK 1
DRAM
WRITE BANK 0
DRAM READ BANK 0 DRAM REFRESH
IDLE
NON·PIPELINED PIPELINED
PIPELINED
PIPELINED
(ALWAYS BOTH
BANKS)
,
1
2 3 1 2 1 2 3
1
2 3
1 2
3
CLK2
~
rvv
~
fV'u
~ ~
~ ~
tv\,
N'u ~ ~ f\A rv-v
f"V'u
CLK
rv-
V- LF ~ ~ w-
kr
l-J
w- ~
w-
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tu-tu-tu-
ADS#
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SELECT
ROWSEL
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L
L-I
L
W
ADDR
XJ.JJ.J.JJ
IXAXXXX X X X X
X X
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RASO#
ROW COLUMN
ROW COLUMN ROW COLUMN
I~
COLUMN
Ir--- REFRESH
RAS1#
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CASx#
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WE#
Ir--
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1,------11
\
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LOW ONLY FIR EN;BLED BYTES
DATA
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XX
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IV'
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DEN#
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REArr--
WRITE
READ
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DT/R#
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NA#
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RFRQ
MUXOE#
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Figure 6-11. 2-CLK DRAM Controller Cycles
DRAM READ BANK 1
PIPELINED
NV ~
tvv
~ ~
~I\
L
w--
X 'IXtJ
ROW
COLUMN
Ir--
II
IL---II
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READIJ
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