Intel 80386

MEMORY INTERFACING
In the 2-CLK design, the four data transceivers are optional because fast DRAMs with
short read-data-float times are used. The DRAM data pins and can
be connected directly to
the
80386 data bus. The strong drive capability of the 80386 data bus can handle the load
of one
DRAM from each bank plus a transceiver load for the other peripherals.
PAL codes and pin descriptions for the 2-CLK design are listed in Appendix C of this manual.
Figure
6-11 shows the timing of DRAM control signals for the 2-CLK design for the follow-
ing
five sequential DRAM cycles:
1. Read cycle
2. Write cycle to the opposite bank (no precharge)
3. Read cycle to that same bank (requires precharge)
4. Refresh cycle (always requires precharge)
5. Read cycle (cycle after refresh always requires precharge)
6.3.4 DRAM Design Variations
Some of the possible variations of the 2-CLK and 3-CLK designs are as follows:
• Both the 3-CLK and 2-CLK designs can use any length DRAM in Nx1 and Nx4 widths.
• Both 3-CLK or 2-CLK designs can use the internal PAL registers or external TTL regis-
ters on the RAS
and/or CAS signals. A conservative design using Nx1 DRAMs might
externally register each RAS (which drives
32 DRAMs) and internally register each CAS
(which drives only
16 DRAMs).
Because internal registers have a greater maximum delay time and potentially less drive, the
choice between registered PALs or external registers affects all of the DRAM timing
parameters based on RAS and CAS. Some of the DRAM parameters are also affected by
the minimum delay time of the internally registered PALs. Because PALs
do not guarantee
a minimum delay time, external
TTL registers, which do guarantee a minimum delay time,
can help meet these timing parameters, as well
as provide greater drive capability.
• Data transceivers are optional for both designs. If a data transceiver is used, the DRAM
read access must meet the 80386 read-data setup time. If no data transceiver is used, the
DRAM read-data-float time must not interfere with the next 80386 cycle, particularly if
it
is a write cycle, and the 80386 data pin loading must not be exceeded.
• By including the column address latch and other circuitry, the DRAM controller can be
adapted to run either 3-CLK or 2-CLK cycles depending on the speed (and cost) of
DRAMs installed. To switch between the 3-CLK and 2-CLK controllers, the user should
plug in a different set of DRAMs, a different
DRAM State PAL, and a different DRAM
Control PAL, and jumper the NA# logic.
• The choice of chip-select logic in both of the designs is arbitrary. Other DRAM memory-
mapping schemes can be implemented by modifying the address decoding to the
DRAM
State PAL chip-selects.
6-23