Intel 80386

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~~===t=============rCLK2 WC~~~~~
1 CAS3
~---+-----------------;:-) WtR ~::~
.",0 CASO
DRAM
CONTROL
L......f> CLK2
oo~
CLK
MeSo
READY I. I " I f""""'-
BUS IDLE --t-----t....-
P--ICS1
CS3
~II i ~ I
Ole J--+--t>o--l
CS2
·'·:fr Q---j.
RFRO
74F138 1---1
DECODER
80386
MICROPROCESSOR
ROWSEL -
DRAM
STATE
PAL
16RSB
MUXOE
DllR
,.so t:!t=t=j
,.s,~ I I I
U;
REFACKO 11 =0 I I
REFACKI RFRO
REfRESH
INTERVAL
COUNTER
PAL
L....--.....J> 20X10A
CLK
PAL
l6RSB
HROWSEL
HOISABLE
~
CLOCK
OE
REFRESH
ADDRESS
COUNTER
PAL
WE 1-1-----------,
DEHt--
DT/R
II 0 0
[co
c"
L.J~
W,
EIGHT
256K ,,1
DRAMs
1
0' SEL p, I I \! I ;
MULTIPLEXED ADDRESS
A20:12I ROW ADDRESS V
V """"";'---L""'L
Al1:3 I COLUMN ADDRESS
74F258
MUXES
"
8E3:0 I
L~~3~is II . i "I
DlIR
II
80386 DATA BUS
74f245
TRANSCEIVERS
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Figure 6-10. 2-CLK DRAM Controller Schematic
A8:0
~ .. ,
,.S
ro-.--,,"
W,
256K" 1
ORAMs
A8:0
DRAM DATA BUS
DINDOUT
CAS I CAS
EIGHT
256Kxl 256K" 1
DRAMs DRAMs
CAS
EIGHT
256K ><,
EIGHT EIGHT
256Kx, 256K x 1 2S6K ><1
DRAMs DRAMs DRAMs
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