MEMORY INTERFACING
3.
Read cycle to that same bank (requires precharge)
4.
Refresh cycle (always requires precharge)
5.
Read cycle (cycle after refresh always requires precharge)
During a normal DRAM access, only the RAS signal that corresponds to the selected bank
is
activated. During a refresh cycle, both RAS signals are activated. During write cycles,
only the CAS signals corresponding to the enabled bytes are activated. During read cycles,
all CAS signals are enabled.
6.3.3.2
2-CLK
DRAM
CONTROLLER
Figure 6-10
is
a schematic of the 2-CLK design, which provides zero wait-state operation
for pipelined interleaved accesses. The design differs from the 3-CLK controller
in
several
ways.
Read and refresh cycles are completed in only two CLKs; write cycles require three CLKs
to ensure that the
80386 write data
is
valid.
In general, the PALs that generate RAS and CAS signals can be either registered or combi-
natorial
on
the RAS
and/or
CAS outputs.
If
external registers are used, these PAL outputs
must be combinatorial
so
that the output has time to set up the external register on the same
CLK2 cycle.
If
the PAL outputs are used without external registers, the PAL outputs must
be registered internally. When the CAS signals are registered internally, the DRAM Control
PAL can sample and save the state of the Byte Enable (BE3#-BEO#) lines internally. When
the CAS signals are registered externally, the
BE3#-BEO# lines must be latched externally
so
that the
DRAM
Control PAL inputs maintain the valid byte enables.
For the 2-CLK design, the RAS and CAS signals are registered externally. The delay (from
CLK2) for these signals
is
reduced, and more time
is
available for the DRAMs to respond.
If
more drive
is
required on these signals, multiple
TTL
registers can be used, each driving
a small group of RAS or CAS lines. For example,
in
a design using
Nxl
DRAMs,
RASO#
must drive
32
DRAMs. To reduce the worst-case
skew
(caused
by
the heavy loading),
RASO#
can be output on four register outputs, each of which drives eight DRAMs.
In the 3-CLK design, the column address does not need to be latched because the Next
Address
(NA#)
signal
is
not activated until after the CAS signals
go
active,
so
the 80386
address remains valid for the memory .access. Because a 2-CLK design has a shorter cycle
time, NA# must be activated before the CAS signals go active to output the next address
one CLK early. This early address necessitates a latch for the column addresses. In many
cases, with a generalized
LE
control, this latch can be shared with the
I/O
subsystem, which
usually must latch the address.
In the 2-CLK design, NA#
is
generated from the DRAM State PAL outputs and
is
there-
fore active in both the CLK2 cycle in which the 80386 samples NA# and the next CLK2
cycle. However, the
80386 does not sample NA# active twice. Once the 80386 outputs the
next address, the address must be valid for
at
least two CLKs before NA#
is
sampled again.
6-21
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