Intel 80386

IDLE DRAM READ BANK 0
DRAM READ BANK 1
DRAM
WRITE BAN K 1
DRAM REFRESH
NON·PIPELINED PIPELINED
PIPELINED
(ALWAYS
BOTH BANKS)
1
2
3
4 1 2
3 1 2
3 4
5 1
2
3 4
CLK2
CLK
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ROW
COLUMN
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RAS1#
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\
LOW ONLY FOR ENABLED BYTES
0
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DATA
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READ
WRITE
DT/R#
RDY
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NA#
I
1\
I
RFRQ
MUXOE#
I
Figure 6-9. 3-ClK DRAM Controller Cycles
5
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