Intel 80386

MEMORY INTERFACING
Four 74F245 octal transceivers buffer the DRAM from the data bus. Most DRAMs used in
the 3-CLK design require these transceivers to meet the read-data float time. When a DRAM
read cycle
is followed immediately by an 80386 write cycle, the 80386 drives its data bus
one CLK2 period after the read cycle completes.
If the data transceivers are omitted, the
RAS inactive delay plus the DRAM output buffer
turn~off time (t-OFF) must be less than
a CLK2 period to avoid data bus contention.
PALs are used to monitor the 80386 status signals and generate the appropriate control
signals for the DRAM, multiplexer, and transceivers.
PAL codes and pin descriptions for
the 3-CLK design are listed
in Appendix C of this manual.
The DRAM State
PAL performs the following functions:
o Monitors the 80386 DRAM chip-select logic
o Receives DRAM refresh requests and responds with the necessary DRAM cycles
o Keeps track of DRAM banks requiring precharge time
A DRAM read or write access
is requested when all the chip-select signals of the DRAM
State
PAL are sampled active simultaneously. These signals become active when all of the
following conditions exist at once:
o MjIO#, W jR#, and DjC# outputs of the 80386 indicate either a memory read, memory
write, or code fetch.
o The bus is idle or the current bus cycle is ending ,(READY # active).
o ADS# is active.
o A31 is low (in this design, the lower half (two gigabytes) of 80386 memory space is
mapped to the DRAM controller).
If the DRAM controller is not already performing a cycle, it begins the access immediately.
However, if the DRAM controller
is performing a refresh cycle, or if it is waiting for the
DRAM bank to precharge, the request is latched and performed when the controller is not
busy.
The
DRAM Control PAL generates the majority of the DRAM control signals. The Refresh
Interval Counter
PAL is a timer that generates refresh requests at the necessary intervals.
The Refresh Address Counter
PAL maintains the next refresh address. Both the Refresh
Interval Counter
PAL and the Refresh Address Counter PAL are simple enough to be
replaced by
TTL counter chips; however, the use of PALs reduces the total chip count. If
there is a spare timer or counter in the system, it can be used to replace one or both of these
PALs.
Figure 6-9 shows the timing of DRAM control signals for the 3-CLK design for the follow-
ing
five sequential DRAM cycles:
1. Read cycle
2. Write cycle to the opposite bank (no precharge)
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