Intel 80386

82384
CLOCK
GENERATOR
CLK
f--
RESET
CLK2
t
•
I
RESET GLK2
NAI-
f--
I
6E3:0
L
READY
P-
BU$IDLE
:Ai5"S
writ
r===u--
.....
ole
...
MliO
AJ1
A2
r-
0>
~
00
80386
MICROPROCESSOR
~ REFACK'
REFACKI
RFRO
REFRESH
INTERVAL
COUNTER
PAL
'----
20X10A
CLK
A1B:11 ROW ADDRESS
Al0:S
COLUMN ADDRESS
031:0
"
CLK2
OTHERREA~
ROY
CLK
. OTHER NA lOGI~
WC
W/R
CAS3
BVTE·ENABlES
iiEiO
CAS2
CAS1
CASO
DRAM
CLK2
CONTROL
CLK
PAL
l6RSe
eso
AOWSEL ROWSEL DEN
-
~
Cs1
MUXOE DISABLE
CTiIt
C53
DRAM
STATE
PAL
1liR8B
Cs<
CS2
A2 RAsa
RFRO RAS1
I
I
>--
41
r-
CLOCK
DE
-
REFRESH
ADDRESS
COUNTER
PAL
laRS
A7:0
~
~}
0'
SOL
11
MULTIPLEXED ADDRESS
74F258
I
MUXES
~
OTIA DON
74F24S
TRANSCEIVERS
Vt-
60386 DATA BUS
DRAM DATA BUS
V
Figure 6-8. 3-CLK DRAM Controller Schematic
,CAS
CAS
ill
WE
DE
A7:0
TWO TWO
64K x4 64Kx4
DRAMs
DRAMs
103:0
RAs
WE
DE
A7:0
TWO TWO
64K ,.4
64Kx4
DRAMs
DRAMs
103:0
CAS
TWO
64K ~ 4
DRAMs
TWO
64K ~ 4
DRr,;"s
CAS
TWO
64Kx4
DRAMs i
TWO
64Kx4
DAAMs
G30107
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