Intel 80386

1/0 INTERFACING
tWA: Address hold after Write (IOWC# rise)
(7 x CLK2 period)
- PAL RegOut Max + PAL RegOut Min
+ Latch Enable Min
(7 x 31.25)
- 12 + 0
+ 5
= 211.75 nanoseconds
tAD:
Data delay from Address
(12 x CLK2 period)
- xcvr. prop Min
(12 x 31.25)
- PAL RegOut Max + Latch Enable Max
- 80386 Data Setup Min
-: 12 - 11.5
- 6
-10
= 335.5 nanoseconds
tRD: Data delay from Read
(IORC#)
(9 x CLK2 period) - PAL RegOut Max - xcvr. prop Min
- 80386 Data Setup Min
(9 x 31.25)
- 12 - 6
-10
= 253.25 nanoseconds
tDF: read
(IORC# rise) to Data Float
(8 x CLK2 period)
- PAL RegOut Max + PAL RegOut Min
+ xcvr. Enable Min
(8 x 31.25) - 12 + 0
+ 3
= 241 nanoseconds
tDW: Data setup before write
(IOWC# rise)
(10 x CLK2 period)
- PAL RegOut Max - xcvr. Enable Max
+ PAL RegOut Min
(10 x 31.25)
- 12 - 11
+ 0
= 289.5 nanoseconds
8-12