1/0
INTERFACING
(A7-A2, and decoded
AI,
AO,
and BHE#) that connect to corresponding inputs of the 82258
must be latched. Because
A7-AO
and BHE# become 82258 outputs after initialization, regis-
tered transceivers (74F543) serve
as
these latches.
ADMA Enable (ADMAEN#)
is
a chip select generated
by
address decoding logic during
80386 accesses to the
I/0
addresses designated for the 82258. The RD# and WR# command
signals from the 80386 bus control logic must be delayed to provide the proper setup time
from chip select to command inputs. This delay can be generated using wait-state generator
signals;
8.6.7
82586
LAN
Coprocessor
The 82586
is
an intelligent, high-performance communications controller designed to perform
most tasks required for controlling access to a local area network (LAN).
In
most applica-
tions, the 82586
is
the communication manager for a station connected to a LAN. Such a
station usually includes a host
CPU, shared memory, a Serial Interface Unit, a transceiver,
and a
LAN
link (see Figure 8-16). The 82586 performs all functions associated with data
transfer between the shared memory and the LAN link, including:
o Framing
• Link management
• Address filtering
• Error detection
• Data encoding
• Network management
• Direct memory access (DMA)
• Buffer chaining
• High-level (user) command interpretation
The 82586 has two interfaces: a bus interface to the 80386 local bus and a network interface
to the Serial Interface
Unit. The bus interface
is
described here. For detailed information
on
using the 82586, refer to the Local Area Networking (LAN) Component User's Manual.
The 82586, which
is
a master
on
the 80386 local bus, communicates directly with the 80386
through the Channel Attention (CA) and interrupt
(INT)
signals. There are several ways
to design an interface between the 82586 and the 80386.
In
general, higher performance
interfaces (requiring less servicing time from the 80386) are more expensive. Four types of
interfaces are described in this section:
• Dedicated CPU
•
Decoupled dual-port memory
• Coupled dual-port memory
• Shared bus
8-27
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