Intel 80386

MUL TIBUS® I AND 80386
Each processor in the multiprocessing system initiates bus cycles as though it has exclusive
use of
MUL TIBUS 1. The bus arbiter keeps track of whether the subsystem has control of
the bus and prevents the bus controller from accessing the bus when the subsystem does not
control the bus.
When the bus arbiter receives control of
MUL TIBUS I, it enables the bus controller and
address latches to drive
MULTI BUS 1. When the transfer is complete, MULTIBUS I returns
the XACK# signal, which activates READY # to end the bus cycle.
9.4.1 Priority Resolution
Because a MUL TIBUS I system includes many bus masters, logic must be provided to resolve
priority between two bus masters that simultaneously request control of
MULTIBUS 1.
Figure 9-7 shows two common methods for resolving priority: serial priority and parallel
priority.
The serial priority technique
is implemented by daisy-chaining the Bus Priority In (BPRN #)
and Bus
Priority Out (BPRO#) signals of all the bus arbiters in the system. Due to delays
in the daisy chain, this technique accommodates only a limited number of bus arbiters.
The parallel priority technique requires external logic to recognize the
BPRN # inputs from
all bus arbiters and return the
BPRO# signal active to the requesting bus arbiter that has
the highest priority. The number of bus arbiters accommodated with this technique depends
on the complexity of the decoding logic.
Priority resolution logic need not be included in the design of a single processing subsystem
with a
MUL TIBUS I interface. The bus arbiter takes control of MUL TIBUS I when the
BPRN# signal goes active and relinquishes control when BPRN# goes inactive. As long as
external logic exists to control the
BPRN# inputs of all bus arbiters, a subsystem can be
designed independent of the priority resolution circuit.
9.4.2 82289 Operating Modes
Following a MULTI BUS I cycle, the controlling bus arbiter can either retain bus control or
release control
so that another bus master can access the bus. Three modes for relinquishing
bus control are
as follows:
• Mode 1- The bus arbiter releases the bus at the end of each cycle.
• Mode 2- The bus arbiter retains control of the bus until another bus master (of any
priority) requests control.
• Mode 3- The bus arbiter retains control of the bus until a higher priority bus master
requests control.
In addition, the bus arbiter can switch between modes 2 and
3, based on the type of bus
cycle.
9-11