Intel 80386

MUL TIBUS® I AND 80386
The BS16# signal is generated and returned to the 80386 for all MULTIBUS I cycles. The
80386 automatically swaps data between the lower half (D15-DO) and the upper half
(D3l- D 16) of its data bus and adds an extra bus cycle as necessary to complete the data
transfer. Therefore, only the logic to swap data from D15-D8 to
D7-DO is needed to meet
the byte-swapping requirement of
MUL TIBUS I.
Figure 9-10 illustrates a circuit that performs the byte-swapping function. The Output Enable
(OE#) inputs of the data latch/transceivers are conditioned by the states of the BHE# and
AO outputs of the address decoder.
9.5.3 Bus Timeout Function for MUL TIBUS® I Accesses
The MULTIBUS I XACK# signal terminates an 80386 bus cycle by driving the wait-state
generator logic. However, if the
80386 addresses a nonexistent device on MUL TIBUS I, the
XACK# signal
is never generated. Without a bus-timeout protection circuit, the 80386 waits
indefinitely for an active
READY # signal and prevents other processors from using
MULTI BUS I.
Figure 9-11 shows an implementation of a bus-timeout circuit that ensures that all
MULTIBUS I cycles eventually end. The ALE# output of the bus controller activates a
one-shot that outputs a I-millisecond pulse. The rising edge of the pulse activates the
TIMEOUT# signal if READY# does not go active within 1 millisecond to clear the
TIMEOUT# flip-flop. The TIMEOUT# signal is input to the wait-state generator logic to
activate the READY # signal. When READY #
goes active, it is returned to clear the
TIMEOUT # signal.
9.5.4 MUL TIBUS® I Power Failure Handling
The MUL TIBUS I interface includes a Power Fail Interrupt PFIN signal to signal an
impending system power failure. Typically,
PFIN# is connected to the non-maskable inter-
rupt
(NMI) request input of each 80386. The NMI service routine can direct the 80386 to
save its environment immediately, before falling voltages and the
MULTIBUS I Memory
Protect (MPRO#) signal prevent any further memory activity. In systems with memory
backup power or nonvolatile memory, the saved environment can be recovered
on powerup.
The power-up sequence of the
80386 can check the state of the MULTI BUS I Power Fail
Sense Latch (PFSN#) to see if a previous power failure has occurred. If this signal is active
(low), the
80386 can branch to a power-up routine that resets the latch using the Power Fail
Sense Reset signal (PFSR#), restores the previous 80386 environment, and resumes
execution.
Further guidelines for designing
80386 systems with power failure features are contained in
the Intel
MULTIBUS® I Specification.
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