Intel 80386

inter
PHYSICAL DESIGN AND DEBUGGING
PAGE
66,132
EQUATES
,
LATCH
EQU
OC8H
; PRESUMES
A HARDWARE
;LATCH IS
AT I/O ADDR
C8H
GOOD SIGNAL
EQU
OAAH
BAD_SIGNAL
EQU
055H
CODE TO VERIFY ABILITY TO l'/RITE AND READ RAM CORRECTLY
INITIAL CODE
READ:
BADRAM:
START:
ASSUME CS:INITIAL CODE
SEGMENT -
ORG
MOV
MOV
MOV
MOV
JMP
CMP
JNE
CMP
JNE
OFOOOH
BX, OOOOH
DS, BX
[BX], 5473H
[BX] +2, 2961H
READ
[BX], 5473H
BADRAM
[BX]+2, 2961H
BAD RAM
;THIS IS INTENDED TO BE LOCATED
;AT PHYSICAL ADDRESS FFFFFOOOH
;INITIALIZE BASE REGISTER TO 0
;INITIALIZE DS REGISTER TO 0
;WRITE 5473H TO RAM ADDR a AND 1
;WRITE
2961H TO RAM ADDR 2 AND 3
;JMP TO FORCE CPU TO BREAK
;PRE-FETCH QUEUE AND FETCH THE
;NEXT INSTRUCTION AGAIN. THIS
;PREVENTS THE RAM DATA WRITTEN
; FROM JUST LINGERING ON THE DATA
;BUS UNTIL THE READ OCCURS
;READ DATA FROM RAM ADDR 0 AND 1
;AND COMPARE WITH VALUE WRITTEN
; IF DATA DOESN-T MATCH, THEN J~IP
;READ DATA FROM RAM ADDR 2 AND 3
;
AND COMPARE WITH VALUE I'IRITTEN
;IF DATA DOESN-T MATCH, THEN JMP
IWV AL, GOOD_SIGNAL
OUT
J~IP
110V
OUT
JMP
ORG
JMP
LATCH, AL
TST_LOOP
AL, BAD SIGNAL
;SIGNAL
THAT DATA \~AS CORRECT
LATCH, AL ;SIGNAL THAT DATA WAS BAD
TST_LOOP
OFFFOH ; POSITION THE FOLLOIHNG INSTRUCTION
;AT OFFSET OFFFOH
TST_LOOP ; INTRA-SEGMENT JUMP (WITHIN
;SEGMENT)
;THIS IS INTENDED TO BE THE FIRST
;INSTRUCTION EXECUTED, SO IT MUST
;BE LOCATED AT PHYSICAL ADDRESS
;FFFFFFFOH.
INITIAL_CODE ENDS
END
Figure 11-12. More Complex Diagnostic Program
11-15