Intel 80386 - Page 278

DRAM PAL DESCRIPTIONS
FUNCTION TABLE
OE CLK2 CLK BEQ BEl BE2 BE3 W";';R ROWSEL DISABLE ; inputs
CASQ CASI CAS2 CAS3 DT%R DEN ROY WC ;outputs
;OE
; 1 CLK2
; 1 1 CLK CASQ
; 1 1 1 BEQ 1 CASI
; 1 1 liBEl 1 1 CAS2
; 1 1 1 1 1 BE2 1 1 1 CAS3
; 1 1 1 1 1 1 BE3 1 1 1 1 DT%R
; 1 1 1 1 1 1 1 W%R 1 1 1 1 1 DEN
; 1 1 1 1 1 1 1 1 ROWSEL 1 1 1 1 1 1 ROY
; 1 1 1 1 1 1 1 1 1 DISABLE 1 1 1 1 1 1 1 WC
;1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
LCHXXXXXHL
LCLXXXXLHL
L C H X X X X H H L
L
C L X X X X L H L
L
C H X X X X X L L
L
C L X X X X X L L
L
C H X X X X X L L
LCLXXXXXLL
L C H X X X X X H L
L
C L X X X X H H L
L
C H X X X X X L L
LCLHLLHXLL
LCHXXXXXLL
LCLXXXXXLL
L C H X X X X X H L
L
C L X X X X L H L
L
C H X X X X X L L
LCLXXXXXLL
L C H X X X X X L L
LCLXXXXXLL
L C H X X X X X H L
L
C L X X X X X H L
LCHXXXXXLH
L C L X X X X X L H
LCHXXXXXLH
L C L X X X X X L L
L
C H X X X X X H L
L
C L X X X X X H L
DESCRI PTION
XXXXXHXL
H H H H L H H L
HHHHHHHL
H H H H L H H L
LLLLLLHH
LLLLLLHH
LLLLLLLH
LLLLLLLL
HHHHLHLL
HHHHHHHL
HHHHHLHH
H L L H H L H H
HLLHHLLH
HLLHHLLL
HHHHHHLL
H H H H L H H L
LLLLLLHH
LLLLLLHH
LLLLLLLH
LLLLLLLL
HHHHLHLL
HHHHXHHL
HHHHXHHL
HHHHXHHL
H H H H X H H L
HHHHXHHL
HHHHXHHL
H H H H X H H L
COMMENTS
initialize to IDLE
IDLE: DT%R tracking W%R
IDLE: DT%R tracking W%R
IDLE: DT%R tracking W";';R
begin read: assert all CAS's
; cont i nue read:
; continue read:
ROY active
; 1 ast read cycl e
;
CAS's and DEN ri se
; DT%R and ROY ri ses
; begi n wri te: assert DEN and WE
; continue write: assert valid CAS's
; cont i nue write: ROY act i ve
; cont i nue wri te:
; CAS's and DEN ri se
; ROY rises
; begi n read: assert all CAS's
cont i nue read:
cont i
nue read: ROY act i ve
last read cycle
CAS's and DEN ri se
ROY ri ses
begin refresh
conti nue refresh
; continue refresh
; last refresh cycle
; IDLE
; IDLE
This PAL implements most of the control signals of the DRAM controller.
Figure C-4. 3-CLK DRAM Control PAL Equations (Cont'd.)
C-16