INTERNAL ARCHITECTURE
2.5
SEGMENTATION UNIT
The Segmentation Unit translates logical addresses into linear addresses
at
the request of
the Execution
Unit. The on-chip Segment Descriptor Cache stores the currently used segment
descriptors to speed this translation.
At
the same time it performs the translation, the
Segmentation
Unit checks for bus-cycle segmentation violations. (These checks are separate
from the static segmentation violation checks performed
by
the Protection Test Unit.) The
translated linear address
is
forwarded to the Paging Unit.
2.6
PAGING UNIT
When the 80386 paging mechanism
is
enabled, the Paging Unit translates linear addresses
generated by the Segmentation
Unit or the Code Prefetch Unit into physical addresses.
(If
paging
is
not enabled, the physical address
is
the same
as
the linear address, and
no
translation
is
necessary.) The Page Descriptor Cache stores recently used Page Directory
and
Page Table entries
in
its Translation Lookaside Buffer (TLB) to speed this translation.
The
Paging Unit forwards physical addresses to the Bus Interface Unit to perform memory
and
I/O
accesses.
2-4
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