Summary Tables of Changes
10
Intel
®
Core™2 Extreme Quad-Core Processor QX6000
Δ
Sequence and Intel
®
Core™2 Quad Processor Q6000
Δ
Sequence
Specification Update
AH = Intel
Core™2 Duo/Solo processor for Intel
Centrino
Duo processor
AI = Intel
Core™2 Extreme processor X6800 and Intel
Core™2 Duo
desktop processor E6000 and E4000 sequence
AJ = Quad-Core Intel
Xeon
processor 5300 series
AK = Intel
Core™2 Extreme quad-core processor QX6000 sequence and
Intel
®
Core™2 Quad processor Q6000 sequence
AL = Dual-Core Intel
Xeon
processor 7100 series
AM = Intel
Celeron
processor 400 sequence
AN = Intel
Pentium
dual-core processor
Quad-Core Intel
®
Xeon
®
processor 3200 series
Dual-Core Intel
®
Xeon
®
processor 3000 series
AQ = Intel
Pentium
dual-core desktop processor E2000 sequence
AR = Intel
Celeron
processor 500 series
Intel
®
Xeon
®
processor 7200, 7300 series
Intel
®
Core™2 Extreme processor QX9650 and Intel
®
Core™2 Quad
processor Q9000 series
Intel
®
Core™ 2 Duo processor E8000 series
AX = Quad-Core Intel
Xeon
processor 5400 series
AY= Dual-Core Intel
Xeon
processor 5200 series
Intel
®
Core™2 Duo Processor and Intel
®
Core™2 Extreme Processor on
45-nm Process
Quad-Core Intel
®
Xeon
®
processor 3300 series
AAB = Dual-Core Intel
Xeon
E3110 Processor
AAC = Intel
Celeron
dual-core processor E1000 series
AAD = Intel
Core™2 Extreme Processor QX9775Δ
Intel
®
Atom™ processor Z5xx series
AAF = Intel
Atom™ processor 200 series
The Specification Updates for the Pentium
®
processor, Pentium
®
Pro processor, and
other Intel products do not use this convention.
NO B3 G0 Plan ERRATA
AK1 X X No Fix
Writing the Local Vector Table (LVT) when an Interrupt is
Pending May Cause an Unexpected Interrupt
AK2 X X No Fix
LOCK# Asserted During a Special Cycle Shutdown
Transaction May Unexpectedly De-assert
AK3 X X No Fix
Address Reported by Machine-Check Architecture (MCA) on
Single-bit L2 ECC Errors May be Incorrect
AK4 X X No Fix
VERW/VERR/LSL/LAR Instructions May Unexpectedly Update
the Last Exception Record (LER) MSR