Errata
Intel
®
Core™2 Extreme Quad-Core Processor QX6000
Δ
Sequence and 21
Intel
®
Core™2 Quad Processor Q6000
Δ
Sequence
Specification Update
Errata
AK1. Writing the Local Vector Table (LVT) when an Interrupt is Pending
May Cause an Unexpected Interrupt
Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may
be taken on the new interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector when a LVT
entry is written, even if the new LVT entry has the mask bit set. If there is
no Interrupt Service Routine (ISR) set up for that vector the system will GP
fault. If the ISR does not do an End of Interrupt (EOI) the bit for the vector
will be left set in the in-service register and mask all interrupts at the same
or lower priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with
it, even if that vector was programmed as masked. This ISR routine must do
an EOI to clear any unexpected interrupts that may occur. The ISR associated
with the spurious vector does not generate an EOI; therefore, the spurious
vector should not be used when writing the LVT.
Status: For the steppings affected, see the Summary Tables of Changes.
AK2. LOCK# Asserted During a Special Cycle Shutdown Transaction May
Unexpectedly De-assert
Problem: During a processor shutdown transaction, when LOCK# is asserted and if a
DEFER# is received during a snoop phase and the Locked transaction is
pipelined on the front side bus (FSB), LOCK# may unexpectedly de-assert.
Implication: When this erratum occurs, the system may hang during shutdown. Intel has
not observed this erratum with any commercially available systems or
software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AK3. Address Reported by Machine-Check Architecture (MCA) on Single-bit
L2 ECC Errors May be Incorrect
Problem: When correctable Single-bit ECC errors occur in the L2 cache, the address is
logged in the MCA address register (MCi_ADDR). Under some scenarios, the
address reported may be incorrect.
Implication: Software should not rely on the value reported in MCi_ADDR, for Single-bit L2
ECC errors.
To Next Page
Loading...
