Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor - Page 32

Errata
32
Intel
®
Core™2 Extreme Quad-Core Processor QX6000
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Sequence and Intel
®
Core™2 Quad Processor Q6000
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Sequence
Specification Update
Implication: (E)CX may contain an incorrect count which may cause some of the MOVS or
STOS operations to re-execute. Intel has not observed this erratum with any
commercially available software.
Workaround: Do not use values in (E)CX that when multiplied by the data size give values
larger than the address space size (64K for 16-bit address size and 4G for
32-bit address size).
Status: For the steppings affected, see the Summary Tables of Changes.
AK31. Performance Monitoring Events for Retired Loads (CBH) and
Instructions Retired (C0H) May Not Be Accurate
Problem: The following events may be counted as instructions that contain a load by
the MEM_LOAD_RETIRED performance monitor events and may be counted
as loads by the INST_RETIRED (mask 01H) performance monitor event:
• Prefetch instructions
• x87 exceptions on FST* and FBSTP instructions
• Breakpoint matches on loads, stores, and I/O instructions
• Stores which update the A and D bits
• Stores that split across a cache line
• VMX transitions
• Any instruction fetch that misses in the ITLB
Implication: The MEM_LOAD_RETIRED and INST_RETIRED (mask 01H) performance
monitor events may count a value higher than expected. The extent to which
the values are higher than expected is determined by the frequency of the
above events.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AK32. Upper 32 bits of 'From' Address Reported through BTMs or BTSs May
be Incorrect
Problem: When a far transfer switches the processor from 32-bit mode to IA-32e
mode, the upper 32 bits of the 'From' (source) addresses reported through
the BTMs (Branch Trace Messages) or BTSs (Branch Trace Stores) may be
incorrect.
Implication: The upper 32 bits of the 'From' address debug information reported through
BTMs or BTSs may be incorrect during this transition
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.