Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor - Page 35

Errata
Intel
®
Core™2 Extreme Quad-Core Processor QX6000
Δ
Sequence and 35
Intel
®
Core™2 Quad Processor Q6000
Δ
Sequence
Specification Update
2) 16-bit addressing in legacy or compatibility mode
Then, depending on the wrap-around point, one of the below saved values may be
corrupted:
• FPU Instruction Pointer Offset
• FPU Instruction Pointer Selector
• FPU Operand Pointer Selector
• FPU Operand Pointer Offset
Implication: This erratum could cause FPU Instruction or Operand pointer corruption and
may lead to unexpected operations in the floating point exception handler.
Workaround: Avoid segment base mis-alignment and address wrap-around at the segment
boundary.
Status: For the steppings affected, see the Summary Tables of Changes.
AK39. Cache Data Access Request from One Core Hitting a Modified Line in
the L1 Data Cache of the Other Core May Cause Unpredictable System
Behavior
Problem: When request for data from Core 1 results in a L1 cache miss, the request is
sent to the L2 cache. If this request hits a modified line in the L1 data cache
of Core 2, certain internal conditions may cause incorrect data to be returned
to the Core 1.
Implication: This erratum may cause unpredictable system behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AK40. PREFETCH Instruction Execution under Some Conditions May Lead to
Processor Livelock
Problem: PREFETCH instruction execution after a split load and dependent upon
ongoing store operations may lead to processor livelock.
Implication: Due to this erratum, the processor may livelock.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AK41. PREFETCH Instructions May Not be Executed when Alignment Check
(AC) is Enabled
Problem: PREFETCHT0, PREFETCHT1, PREFETCHT2 and PREFETCHNTA instructions may
not be executed when Alignment Check is enabled.
Implication: PREFETCH instructions may not perform the data prefetch if Alignment Check
is enabled.