Errata
Intel
®
Core™2 Extreme Quad-Core Processor QX6000
Δ
Sequence and 39
Intel
®
Core™2 Quad Processor Q6000
Δ
Sequence
Specification Update
results in a debug exception being signaled on an unexpected instruction
boundary since the MOV SS/POP SS and the following instruction should be
executed atomically.
Implication: This can result in incorrect signaling of a debug exception and possibly a
mismatched Stack Segment and Stack Pointer. If MOV SS/POP SS is not
followed by a MOV [r/e]SP, [r/e]BP, there may be a mismatched Stack
Segment and Stack Pointer on any exception. Intel has not observed this
erratum with any commercially available software, or system.
Workaround: As recommended in the IA32 Intel
®
Architecture Software Developer’s
Manual, the use of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP
will avoid the failure since the MOV [r/e]SP, [r/e]BP will not generate a
floating point exception. Developers of debug tools should be aware of the
potential incorrect debug event signaling created by this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AK52. Last Branch Records (LBR) Updates May be Incorrect after a Task
Switch
Problem: A Task-State Segment (TSS) task switch may incorrectly set the LBR_FROM
value to the LBR_TO value.
Implication: The LBR_FROM will have the incorrect address of the Branch Instruction.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AK53. IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly
Problem: The IO_SMI bit in SMRAM's location 7FA4H is set to "1" by the processor to
indicate a System Management Interrupt (SMI) occurred as the result of
executing an instruction that reads from an I/O port. Due to this erratum, the
IO_SMI bit may be incorrectly set by:
• A non-I/O instruction.
• SMI is pending while a lower priority event interrupts
• A REP I/O read
• An I/O read that redirects to MWAIT
• In systems supporting Intel
®
Virtualization Technology a fault in the middle of an
I/O operation that causes a VM Exit
Implication: SMM handlers may get false IO_SMI indication.
Workaround: The SMM handler has to evaluate the saved context to determine if the SMI
was triggered by an instruction that read from an I/O port. The SMM handler
must not restart an I/O instruction if the platform has not been configured to
generate a synchronous SMI for the recorded I/O port address.
Status: For the steppings affected, see the Summary Tables of Changes.
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