Summary Tables of Changes
16 Specification Update
Errata
EFLAGS Discrepancy on a Page Fault After a Multiprocessor
TLB Shootdown
INVLPG Operation for Large (2M/4M) Pages May be
Incomplete under Certain Conditions
Store to WT Memory Data May be Seen in Wrong Order by
Two Subsequent Loads
Non-Temporal Data Store May be Observed in Wrong
Program Order
Page Access Bit May be Set Prior to Signaling a Code
Segment Limit Fault
Updating Code Page Directory Attributes without TLB
Invalidation May Result in Improper Handling of Code #PF
Storage of PEBS Record Delayed Following Execution of
MOV SS or STI
Performance Monitoring Event FP_MMX_TRANS_TO_MMX
May Not Count Some Transitions
A REP STOS/MOVS to a MONITOR/MWAIT Address Range
May Prevent Triggering of the Monitoring Hardware
Performance Monitoring Event MISALIGN_MEM_REF May
Over Count
The Processor May Report a #TS Instead of a #GP Fault
Code Segment Limit Violation May Occur on 4 Gigabyte
Limit Check
A Write to an APIC Register Sometimes May Appear to
Have Not Occurred
Last Branch Records (LBR) Updates May be Incorrect after
a Task Switch
REP MOVS/STOS Executing with Fast Strings Enabled and
Crossing Page Boundaries with Inconsistent Memory Types
may use an Incorrect Data Size or Lead to Memory-
Ordering Violations.
Upper 32 bits of 'From' Address Reported through BTMs or
BTSs May be Incorrect
Address Reported by Machine-Check Architecture (MCA) on
Single-bit L2 ECC Errors May be Incorrect
Code Segment Limit/Canonical Faults on RSM May be
Serviced before Higher Priority Interrupts/Exceptions
Store Ordering May be Incorrect between WC and WP
Memory Type
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