Summary Tables of Changes
Specification Update 17
EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect
after Shutdown
Premature Execution of a Load Operation Prior to Exception
Handler Invocation
Performance Monitoring Events for Retired Instructions
(C0H) May Not Be Accurate
Returning to Real Mode from SMM with EFLAGS.VM Set May
Result in Unpredictable System Behavior
CMPSB, LODSB, or SCASB in 64-bit Mode with Count
Greater or Equal to 248 May Terminate Early
Writing the Local Vector Table (LVT) when an Interrupt is
Pending May Cause an Unexpected Interrupt
Pending x87 FPU Exceptions (#MF) Following STI May Be
Serviced Before Higher Priority Interrupts
VERW/VERR/LSL/LAR Instructions May Unexpectedly
Update the Last Exception Record (LER) MSR
INIT Does Not Clear Global Entries in the TLB
Split Locked Stores May not Trigger the Monitoring
Hardware
Programming the Digital Thermal Sensor (DTS) Threshold
May Cause Unexpected Thermal Interrupts
Writing Shared Unaligned Data that Crosses a Cache Line
without Proper Semaphores or Barriers May Expose a
Memory Ordering Issue
General Protection (#GP) Fault May Not Be Signaled on
Data Segment Limit Violation above 4-G Limit
An Asynchronous MCE During a Far Transfer May Corrupt
ESP
CPUID Reports Architectural Performance Monitoring
Version 2 is Supported, When Only Version 1 Capabilities
are Available
B0-B3 Bits in DR6 May Not be Properly Cleared After Code
Breakpoint
An xTPR Update Transaction Cycle, if Enabled, May be
Issued to the FSB after the Processor has Issued a Stop-
Grant Special Cycle
Performance Monitoring Event IA32_FIXED_CTR2 May Not
Function Properly when Max Ratio is a Non-Integer Core-
to-Bus Ratio
Instruction Fetch May Cause a Livelock During Snoops of
the L1 Data Cache
Use of Memory Aliasing with Inconsistent Memory Type
may Cause a System Hang or a Machine Check Exception
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