Summary Tables of Changes
18 Specification Update
A WB Store Following a REP STOS/MOVS or FXSAVE May
Lead to Memory-Ordering Violations
VM Exit with Exit Reason "TPR Below Threshold" Can Cause
the Blocking by MOV/POP SS and Blocking by STI Bits to be
Cleared in the Guest Interruptibility-State Field
Using Memory Type Aliasing with Cacheable and WC
Memory Types May Lead to Memory Ordering Violations
VM Exit Caused by a SIPI Results in Zero Being Saved to
the Guest RIP Field in the VMCS
NMIs May Not Be Blocked by a VM-Entry Failure
Partial Streaming Load Instruction Sequence May Cause
the Processor to Hang
Self/Cross Modifying Code May Not be Detected or May
Cause a Machine Check Exception
Data TLB Eviction Condition in the Middle of a Cacheline
Split Load Operation May Cause the Processor to Hang
Update of Read/Write (R/W) or User/Supervisor (U/S) or
Present (P) Bits without TLB Shootdown May Cause
Unexpected Processor Behavior
RSM Instruction Execution under Certain Conditions May
Cause Processor Hang or Unexpected Instruction Execution
Results
Benign Exception after a Double Fault May Not Cause a
Triple Fault Shutdown
LER MSRs May Be Incorrectly Updated
Processor May Unexpectedly Assert False THERMTRIP#
After Receiving a Warm Reset
Short Nested Loops That Span Multiple 16-Byte Boundaries
May Cause a Machine Check Exception or a System Hang
IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine
Check Error Reporting Enable Correctly
An Enabled Debug Breakpoint or Single Step Trap May Be
Taken after MOV SS/POP SS Instruction if it is Followed by
an Instruction That Signals a Floating Point Exception
Code Segment Limit/Canonical Faults on RSM May be
Serviced before Higher Priority Interrupts/Exceptions and
May Push the Wrong Address Onto the Stack
A VM Exit Due to a Fault While Delivering a Software
Interrupt May Save Incorrect Data into the VMCS
A VM Exit Occurring in IA-32e Mode May Not Produce a
VMX Abort When Expected
IRET under Certain Conditions May Cause an Unexpected
Alignment Check Exception