Intel T8300 - Core 2 Duo 2.4GHz 800MHz 3MB Socket P Mobile CPU - Specification Changes

Summary Tables of Changes
Specification Update 19
Number
Steppings
Status
ERRATA
C-0
M-0
E-0
R-0
AZ60
X
X
X
X
No Fix
Thermal Interrupts are Dropped During and While Exiting
Intel® Deep Power-Down State
AZ61
X
X
X
X
No Fix
VM Entry May Fail When Attempting to Set
IA32_DEBUGCTL.FREEZE_WHILE_SMM_EN
AZ62
X
X
No Fix
VM Entry May Use Wrong Address to Access Virtual-APIC
Page
AZ63
X
X
No Fix
INIT Incorrectly Resets IA32_LSTAR MSR
AZ64
X
X
No Fix
When a CPUID instruction is executed, the returned EAX,
EBX, ECX, and/or EDX may be incorrect.
AZ65
X
X
X
X
No Fix
Global Instruction TLB Entries May Not be Invalidated on a
VM Exit or VM Entry
AZ66
X
X
No Fix
XRSTOR Instruction May Cause Extra Memory Reads
AZ67
X
X
X
X
No Fix
LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode
AZ68
X
X
No Fix
When Intel® Deep Power-Down State is Being Used,
IA32_FIXED_CTR2 May Return Incorrect Cycle Counts
AZ69
X
X
No Fix
Enabling PECI via the PECI_CTL MSR Incorrectly
Writes CPUID_FEATURE_MASK1 MSR
AZ70
X
X
X
X
No Fix
Corruption of CS Segment Register During RSM While
Transitioning From Real Mode to Protected Mode
AZ71
X
X
No Fix
The XSAVE Instruction May Erroneously Set Reserved Bits
in the XSTATE_BV Field
AZ72
X
X
No Fix
Store Ordering Violation When Using XSAVE
AZ73
X
X
X
X
No Fix
Memory Ordering Violation With Stores/Loads Crossing a
Cacheline Boundary
AZ74
X
X
No Fix
The XRSTOR Instruction May Fail to Cause a General-
Protection Exception
AZ75
X
X
X
X
No Fix
B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be
Incorrectly Set
AZ76
X
X
X
X
No Fix
A 64-bit Register IP-relative Instruction May Return
Unexpected Results
AZ77
X
X
X
X
No Fix
Intel® Trusted Execution Technology ACM Revocation
Number
SPECIFICATION CHANGES
There are no Specification Changes in this Specification Update revision