Errata
Specification Update 25
AZ10. Performance Monitoring Event MISALIGN_MEM_REF May Over Count
Problem: Performance monitoring event MISALIGN_MEM_REF (05H) is used to count the number
of memory accesses that cross an 8-byte boundary and are blocked until retirement. Due
to this erratum, the performance monitoring event MISALIGN_MEM_REF also counts
other memory accesses.
Implication: The performance monitoring event MISALIGN_MEM_REF may over count. The extent of
the over counting depends on the number of memory accesses retiring while the counter
is active.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AZ11. The Processor May Report a #TS Instead of a #GP Fault
Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception)
instead of a #GP fault (general protection exception).
Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP
fault. Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AZ12. Code Segment Limit Violation May Occur on 4-Gigabyte Limit Check
Problem: Code Segment limit violation may occur on 4-Gigabyte limit check when the code stream
wraps around in a way that one instruction ends at the last byte of the segment and the
next instruction begins at 0x0.
Implication: This is a rare condition that may result in a system hang. Intel has not observed this
erratum with any commercially available software, or system.
Workaround: Avoid code that wraps around segment limit.
Status: For the steppings affected, see the Summary Tables of Changes.
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