Errata
26 Specification Update
AZ13. A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
Problem: With respect to the retirement of instructions, stores to the uncacheable memory-based
APIC register space are handled in a non-synchronized way. For example if an instruction
that masks the interrupt flag, e.g., CLI, is executed soon after an uncacheable write to
the Task Priority Register (TPR) that lowers the APIC priority, the interrupt masking
operation may take effect before the actual priority has been lowered. This may cause
interrupts whose priority is lower than the initial TPR, but higher than the final TPR, to
not be serviced until the interrupt enabled flag is finally set, i.e. by STI instruction.
Interrupts will remain pending and are not lost.
Implication: In this example the processor may allow interrupts to be accepted but may delay their
service.
Workaround: This non-synchronization can be avoided by issuing an APIC register read after the APIC
register write. This will force the store to the APIC register before any subsequent
instructions are executed. No commercial operating system is known to be impacted by
this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AZ14. Last Branch Records (LBR) Updates May Be Incorrect after a Task
Switch
Problem: A Task-State Segment (TSS) task switch may incorrectly set the LBR_FROM value to the
LBR_TO value.
Implication: The LBR_FROM will have the incorrect address of the Branch Instruction.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
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