Intel T8300 - Core 2 Duo 2.4GHz 800MHz 3MB Socket P Mobile CPU - Page 49

Errata
Specification Update 49
AZ66. XRSTOR Instruction May Cause Extra Memory Reads
Problem: An XRSTOR instruction will cause non-speculative accesses to XSAVE memory area
locations containing the FCW/FSW and FOP/FTW Floating Point registers even though the
64-bit restore mask specified in the EDX:EAX register pair does not indicate to restore
the x87 FPU state.
Implication: Page faults, data breakpoint triggers, etc. may occur due to the unexpected
nonspeculative accesses to these memory locations.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AZ67. LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode
Problem: An exception/interrupt event should be transparent to the LBR (Last Branch Record), BTS
(Branch Trace Store) and BTM (Branch Trace Message) mechanisms. However, during a
specific boundary condition where the exception/interrupt occurs right after the
execution of an instruction at the lower canonical boundary (0x00007FFFFFFFFFFF) in 64-
bit mode, the LBR return registers will save a wrong return address with bits 63 to 48
incorrectly sign extended to all 1s. Subsequent BTS and BTM operations which report
the LBR will also be incorrect.
Implication: LBR, BTS and BTM may report incorrect information in the event of an
exception/interrupt.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AZ68. When Intel® Deep Power-Down State is Being Used, IA32_FIXED_CTR2
May Return Incorrect Cycle Counts
Problem: When the processor is operating at an N/2 core to front side bus ratio, after exiting an
Intel Deep Power-Down state, the internal increment value for IA32_FIXED_CTR2 MSR
(Fixed Function Performance Counter 2, 30BH) will not take into account the half ratio
setting.
Implication: Due to this erratum, IA32_FIXED_CTR2 MSR will not return reliable counts after
returning from an Intel Deep Power-Down state.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.