Errata
Specification Update 51
AZ72. Store Ordering Violation When Using XSAVE
Problem: The store operations done as part of the XSAVE instruction may cause a store ordering
violation with older store operations. The store operations done to save the processor
context in the XSAVE instruction flow, when XSAVE is used to store only the SSE context,
may appear to execute before the completion of older store operations.
Implication: Execution of the stores in XSAVE, when XSAVE is used to store SSE context only, may
not follow program order and may execute before older stores. Intel has not observed
this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AZ73. Memory Ordering Violation With Stores/Loads Crossing a Cacheline
Boundary
Problem: When two logical processors are accessing the same data that is crossing a cacheline
boundary without serialization, with a specific set of processor internal conditions, it is
possible to have an ordering violation between memory store and load operations.
Implication: Due to this erratum, proper load store ordering may not be followed when multiple
logical processors are accessing the same data that crosses a cacheline boundary without
serialization.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AZ74. The XRSTOR Instruction May Fail to Cause a General-Protection
Exception
Problem: The XFEATURE_ENABLED_MASK register (XCR0) bits [63:9] are reserved and must be 0;
consequently, the XRSTOR instruction should cause a general-protection exception if any
of the corresponding bits in the XSTATE_BV field in the header of the XSAVE/XRSTOR
area is set to 1. Due to this erratum, a logical processor may fail to cause such an
exception if one or more of these reserved bits are set to 1.
Implication: Software may not operate correctly if it relies on the XRSTOR instruction to cause a
general-protection exception when any of the bits [63:9] in the XSTATE_BV field in the
header of the XSAVE/XRSTOR area is set to 1.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AZ75. B0-B3 Bits in DR6 for Non-Enabled Breakpoints May be Incorrectly Set
Problem: Some of the B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may be
incorrectly set for non-enabled breakpoints when the following sequence happens:
1. MOV or POP instruction to SS (Stack Segment) selector;
2. Next instruction is FP (Floating Point) that gets FP assist
3. Another instruction after the FP instruction completes successfully
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