Errata
52 Specification Update
4. A breakpoint occurs due to either a data breakpoint on the preceding instruction or a
code breakpoint on the next instruction.
Due to this erratum a non-enabled breakpoint triggered on step 1 or step 2 may be
reported in B0-B3 after the breakpoint occurs in step 4.
Implication: Due to this erratum, B0-B3 bits in DR6 may be incorrectly set for non-enabled
breakpoints
Workaround: Software should not execute a floating point instruction directly after a MOV SS or POP
SS instruction
Status: For the steppings affected, see the Summary Tables of Changes.
AZ76. A 64-bit register IP-relative instruction may Return unexpected Results
Problem: Under an unlikely and complex sequence of conditions in 64-bit mode, a register IP-
Relative instruction may be incorrect.
Implication: A register IP-relative instruction result may be incorrect and could cause software to read
from or write to an incorrect memory location. This may result in an unexpected page fault
or unpredictable system behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes
AZ77. Intel Trusted Execution Technology ACM Revocation
Problem: SINT ACM GM45_GS45_PM45_SINIT_21.BIN or Earlier are revoked and will not launch
with the processor configuration information.
Implication: Due to this erratum, SINT ACM GM45_GS45_PM45_SINIT_21.BIN and earlier will be
revoked.
Workaround: It is possible for the BIOS to contain a workaround for this erratum. All Intel TXT enabled
software must use SINT ACM GM45_GS45_PM45_SINIT_51.BIN or later.
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