JVC FS-SD58V - Page 34

FS-SD58V/FS-SD78V/FS-SD98V
1-34
2.Block diagram
TEST
V DD
GND
PCL
Display control data register
Output controller
Back- ground control data register
Video RAM
Out- put speci- fication data 1 bit x 288 words
Re- verse data 1 bit x 288 words
Blink data 1 bit x 288 words
Color data 3 bits x 288 words
Char- acter data 8 bits x 288 words
Data selector
Control signals
Instruction decoder
Horizontal size counter
Character size register
Data input shift register
Horizontal position counter
Horizontal address register for display position
Horizontal address counter
Write address counter
Vertical address register for display position
Vertical address counter
Character generator ROM 12 x 18 bits x 256 words
Veritical position counter
Veritical size counter
Synchro nization protaction circuit
Oscil- lator
Vsync Hsync CK
OUT
OSC
IN
OSC
OUT
CS
CLK
DATA
V
R
V
G
V
B
V
BLK
V
C1
BLK1 V
C2
BLK2
1
2
3
4
5
6
7
8
9
10
CLK
CS
DATA
PCL
VDD
CKOUT
OSCOUT
OSCIN
TEST
GND
Hsync
Vsync
VE
VG
VR
VBLK(BBLK)
VC2(GBLK)
BLK2(RBLK)
VC1
BLK1
20
19
18
17
16
15
14
13
12
11
UPD6461GS-635(IC06):OSD
1.Terminal layout