JVC FS-SD7R - Page 32

FS-SD5R/FS-SD7R/FS-SD9R
mM LA6541-X (IC602) : Servo driver
1. Pin Layout & Block Diagram
Vcc Vref Vind Vg4 ae Vo7 Vo6 Vo5 Vg3-sCVin3 Cd Res
3 fig [18] 7’
41k
ohm
BTL BTL Level
i driver driver i RESET
BTL BTL
driver driver
TE
11k
ohm
1 2 [5] 6s. L
Vcc Mute Vint Vgi Vol Vo2 Gnd es Vin2 Re Reg
ou n
2. Pin functions
Function
Power supply (Shorted to pin 24)
2 All BTL amplifier outputs ON/OFF
3 Vin4 BTL AMP 1 input pin
4 Vg1 BTL AMP 1 input pin (For gain adjustment)
5 Vot BTL AMP 1 input pin (Non inverting side)
6 Vo2 BTL AMP 1 input pin (Inverting side)
7 Vo3 BTL AMP 2 input pin (Inverting side)
8
Vo4 BTL AMP 2 input pin (Non inverting side)
9 vee [BTL AMP 2 input pin (For gain adjustment)
10 Vin2 BTL AMP 2 input pin
11 Reg Out | External transistor collector (PNP) connection. 5V power supply output
12 Reg In | External transistor (PNP) base connection
13 Res Reset output
14 Cd Reset output delay time setting (Capacitor connected externally)
15 Vin3 BTL AMP 3 input pin
16 Vg3 BTL AMP 3 input pin (For gain adjustment)
17 | Vo5 BTL AMP 3 output pin (Non inverting side)
18 Vo6 BTL AMP 8 output pin (Inverting side)
19 Vo7 BTL AMP 4 output pin (Inverting side)
20 Vo8 BTL AMP 4 output pin (Non inverting side)
21 Vg4 BTL AMP 4 output pin (For gain adjustment)
22 Vin4 | BTL AMP 4 output pin
23 vret_| Level shift circuit's reference voltage application
24 Vcc Power supply (Shorted to pin 1)
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