JVC FS-SD7R - Page 33

FS-SD5R/FS-SD7R/FS-SD9R
M@ LC72136N (IC2) : PLL frequency synthesizer
1. Pin layout
FM/ST'VCO
AM/FM
1
2
3
4
5
6
7
8
9
1
1
-O SDIN
2. Block diagram
Phase
Detector
Charge Pump
Unlock
Detector '
t
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t
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C= Data Shift Register & Latch Ca
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3. Pin function
No Symbol | I/O Function . | Symbol | I/O Function
1 XT | | X'tal oscillator connect (75kHz) IFIN | | IF counter signa! input
[2 | FM/AM | © | LOW:FM mode IFCONT | O | IF signal output
3 rf CE | | When data output/input for 4pin(input) and - | Not use
6pin(output): H ses
4 DI | | Input for receive the serial data from AMIN | | AM Local OSC signal output
| controlier
5 |. CLOCK | | Sync signal input use FMIN 1 | FM Local OSC signal input
6 DO © | Data output for Controller VCC - | Power suplly(VDD=4.5-5.5V)
| Output port When power ON:Reset circuit move
7 eae O | "Low": MW mode PD O | PLL charge pump output(H: Local OSC
frequency Height than Reference frequency.
L: Low Agreement: Height impedance)
8 iG AM/EM © | Open state after the power on reset LPFIN | | Input for active lowpassfilter of PLL
| 9 LW V/O | input/output port LPFOUT | O | Output for active lowpassfilter of PLL
10 Mw /O | Input/output port GND -_| Connected to GND |
11 SDIN V/O | Data input/output XT | | X'tal osciliator(75KHz)
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