JVC FS-SD7R - Page 37

FS-SD5R/FS-SD7R/FS-SD9R
lM BU1923(IC4) : RDS detector
1.Terminal Layout 2.Pin Function
a
z [oe [oe [rosea
[rer | 0 |patencevoeecupt
wot tiered
Es
Ex
ce
ai
QUAL
DA
VREF
MUX
| voo | +5Vsupply voltage for analog
Ground for analog part(OV)
Sub carrier output of reconstruction filter
VDD
GND
CIN
OUT
Ground for digital part(OV)
Ground for digital part(OV)
ce
[= [eransiorsoinpanoy
= [evainsior sata panon
= [svaioy vote trainer |
To [osctrouma iS
= [nencomtin i
Es
RDS clock output
D
M
Vv
G
Cc
oO
G
G
Vv
X
T
A
UX
DD
ND
IN
UT
ND
ND
ND
DD
Xl
O
S7
CL
= = = = i =? =?
3.Block Diagram
ANI- 5kHz RECONSTRUCTION OSCILLATOR DUALITY BIT
ALIADING BANDPASS FILTER AND GENERATOR
FILTER (8th ORDER) x DIVIDER
COSTAS LOOP BIPHASE
CLOCKED VARIABLE AND SYMBOL
COMPARATOR
FIXWD
DIVIDER
DECODER
REFERENCE - Praeire aii TEST LOGIC AND OUTPUT
VOLTEGE AND SYNC SELECTOR SWITCH
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