JVC GR-DVL725U - Page 102

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2
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5
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ABCD EFGH
4-744-73
REGULATOR SYSTEM BLOCK DIAGRAM4.35
L6101
L6102
REG_3V
F6101
Q6001
R6002
R6001
Q6002(1/2)
R6004
IC6001
Q6002(2/2)
R6003
ADP_DC
ADP_DC
BATT_+
BATT_+
CN104CN552
CN103CN551
3
2
1
4
5
6
H :ON
H :ON
LAMP ON
DRUM
POWER
CAPSTAN
POWER
3V
SW REG
Q6201,
L6201, C6202
1.8V
SW REG
DRUM_PWR
DRUM_ERR
CAP_PWR
CAP_ERR
VF
4.8V
SW REG
ES
VF_CTL
REG_4.8V
SW REG
VCC1
OUT4
L :STOP
H :START
DC-DC CONV
CTL
L :ON
at POWER OFF
BATT DC DET
1
DET:L
2
POWER ON:H
POWER OFF:ON
REG
12V
DIF
AMP
VCC2
REG_1.8V
CN101
REG_4.8V
CN101
REG_4.8V
REG_4.8V
AMP
DIF
-CCD
REG
6
10 MAIN(REG)
13
21
14
BATT
47
SHUTDOWN
IN9-
IN8-
IN9+
60
OUT7P
R6701
IC6101
Q6701
L6701, C6703
POWER CTL
8
54
OUT5
53
OUT1
58
OUT2
57
51
IN4-
IN4+
32
31
IN5-
IN5+
35
IN1-
23
OUT11
50
IN11-
48
IN2-
25
OUT3
56
IN3-
27
OUT6
55
IN6-
29
OUT10
62
IN10-
63
34
Q6217
Q6208,
L6206, C6215
Q6210,
L6207, C6218
C6221
AL3V
SW REG
REG_2.5V
REG_3V
REG_3V
REG_3V
CN106
LAMP_4.5V
M_UNREG
2.5V
SW REG
CN105
16
CN109
2
33
M_REG4.8V
15 16
30
L6204
CN102
19
Q6212 Q6213
REG_12V
32
REG_12V
CN101
19
18
Q6215 Q6216
D6206
Q6207
Q6205
Q6206
VFREG4.8
CN101
REG_15V
REG-CCD
D_GAIN
REG4.8
REG_-15V
153
151
VF_CTL
LAMP ON
VF_CTL
V_BATT
AL_3V
78
RESET
IC1001(CPU)
T_BATT
ADP_H
8
VDD
128
RESET
IC1008
12
IC1002
45
56
L1002
AL_3V
D6002
REAR
(SYSCON)
MONITOR
BT1
02
ADP_DC IN
T
BATT.TERM
07
R6005
LITHIUM
LITHIUM
33
CN761
8
CN101
R6705
T_BATT
ADP_H
12
11
1
2
ADP_DC
10
2
1
3
BATT_CHK
3
GND
GND
5
6
4
R6704
T_BATT
L6205
C6227
D6208
Q6202,
R6206, C6204
Q6203,
L6202, C6207
Q6204,
L6203, C6210
Q6211, L6208
Q6004, C6004
(Sanwa)-M2D229/249/2L9 GR-DVL725U, DVL820U, DVL920U
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