JVC GR-SXM277UA - Page 94

5
4
3
2
1
A
BC
D
MONITOR SYSTEM BLOCK DIAGRAM
-
+
MODE SEL
V.SYNC H.SYNC
FIELD
DET
POL
CTL
PHASE
COMP
SEL
QVD
EQ
PULSE
CANCEL
VCO
VCOI
36
QVD
34
PD
33
37
JUST
31
HDOT2
30
CPH1
29
RL
28
CPH2
27
CPH3
25
STV2
26
24STH2
STH1 23
22
QH
OEH
21
STV1
20
RESET
38
39
40
48
NC
18
OEV2
17
CPV 16
INT/EXT 15
POL 14
UD 13
NC
1
HD_IN
23
QH_SEL
4
VDB_IN
56
HD_OUT
NC
7
NC
812
7
5
6
R7612
L7605
ROUT
GOUT
BOUT
BUF&SW
Q7001
Q7002
Q7003
Q7001
Q7005
Q7003
RVS_SW
FROM DSP
IC7602
IC7601
COUNTER
ZOOM
CORRECT
8
11
10
1
18
15
16
25
VDCVF
HDCVF
DSP_REST
C7617
R7607
REG_3.2V
6
10
OSCCTL
Q7504 Q7502
Q7501Q7503
F7501
T7501
OSC
2
3
4
1
CTL
Q7504 Q7502
Q7501Q7503
F7501
T7501
LCD (DAC_3.2V)
6
DSP_REST
FROM CPU
7
19
PMIRROR
PMIRROR
HDCVF
FROM DSP
VDCVF
5
LCD_CTL
FROM CPU
REG_4.8V
FROM REG
MAIN10
9
HRP1
17
REV_SW
HRP1
FROM CPU
TO DSP
LCD_CTL
REG_4.8V
REG_4.8V
CN7601CN16
4
21
20
22
CVF
CFL
NC
LT
Q7608
SW
BUF&SW
BUF&SW
BUF&SW
BUF&SW
BUF&SW
IC7604
3
2
1
2-51