JVC KD-S777R - Page 15

UPD178076GF (IC701): SYSTEM CPU
1.Terminal layout
2.Block diagram
1
30
~
80
51
~
100 ~ 81
31 ~ 50
8-bit TIMER/
EVENT COUNTER 1
8-bit TIMER/
EVENT COUNTER 0
WATCHDOG TIMER
BASIC TIMER
SERIAL
INTERFACE 0
TO0/VTR-CONT
TI00/POWER
TI01/CD-ON
TI50/MUTE
TO50/NC
TI51/STAGE
TO51/NC
SI0/SB0/SDA0/NC
SO0/SB1/SDA1/VOL-DA
SCK0/SCL/VOL-CLK
SI1/JBUS-SI
SO1/JBUS-SO
SCK1/JBUS-SCK
STB/NC
BUSY/NC
SI3/NC
SO3/LCD-DA
SCK3/SCL/LCD-CLK
RESET
CPU
PERIPHERAL
VOSC
VCPU
TXD0/LM1
RXD0/LM0
INTP0/NC
INTP7/NC
VM45/VTR-LOGIC
REGOSC
REGCPU
GND0
GND1
BEEP0/BUZZER
BUZ/JAPAN
RESET
X1
X2
VDDPORT
GNDPORT
VDD
SERIAL
INTERFACE 1
SERIAL
INTERFACE 3
UART0
8
INTERRUPT
CONTROL
BUZER OUTPUT
SYSTEM
CONTROL
VOLTAGE
REGULATOR
PLL
VOLTAGE
REGULATOR
PLL
FREQUENCY
COUNTER
A/D
CONVERTER
PORT 13
PORT 12
PORT10
PORT 7
PORT 6
PORT 5
PORT 4
PORT 3
PD178078
:3Kbyte
PD178076
:2Kbyte
RAM
PD178078
:60Kbyte
PD178076
:48Kbyte
RAM
78k/0
CPU
CPRE
16-bit TIMER/
EVENT COUNTER
PORT 0
PORT 1
PORT 2
8
8
8
8
8
8
8
8
8
8
3
5
NC,JBUS-INT,SW1,
REMOCON,PS1,PS2,
DETACH,NC
KEY0,KEY1,KEY2,LEVEL,
SM,SQ,
JBUS-SI,JBUS-SO,
JBUS-SCK,12CDAI,
12CDAO,12CCLK
VTR-LOGIC,VTR-CONT,
POWER,CD-ON,MUTE,
STAGE,BUZZER,JAPAN
NC
NC,LCD-CE,SW2,SW3,
SW4,RST-SW,ENC1,ENC2
MONO,SEEK/STOP,
FM/AM,NC,
NC,LCD-DA,LCD-CLK,
JBUS-/O,LM0,LM1,BUCK,
CCE
SD/ST,NC,IFC
BUS0,BUS1,BUS2,BUS3,
RST
NC
AN10/KEY0
AN17/NC
AMIFC/NC
FMIFC/IFC
EO1
EO0
VCOL
VCOH
VDDPLL
GNDPLL
IC
GND2
AVDD
AVSS
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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