JVC MX-J30 - Page 22

MX-J30/MX-J330/MX-J35R
@ BU1923(IC4) : RDS Detector
1.Terminal
Layout
2.Pin
Functiont
Symbol
VO
Function
UAL
Zz
QUAL on connection
DA
DS
data
output
VREF
DD
eference voltage output
>
|
VREF
sis
MUX
rai
Multiplex
signal
input
[yoo
|=
[svar
wtssetoraraig
a
[eno
|
=
[eeunstranaeapanoy
-
on
[1
[Siew
cupteeoentin
ter
7
ouT
|
©
[omatragiapanoy
|
our
eno
[=
[Seusiorsatanenon
Ground for digital part(OV)
G Ground for digital part(OV)
g
S\S
nD
<
S
S)
+5Vsupply voltage for digital part
Oscilator input
Oscilator output
—_
a
wn
N 4
x<
Non connection
ad
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RDS clock output
3.Block Diagram
Aone Serisnics RECONSTRUCTION OsdIt ATOR) | GuaLiTy BIT
pee GENETATOR
FILTER
(8th
ORDER)
DIVIDER
1
COSTAS LOOP BIPHASE
VLOEKED
VARRIABLE
AND
SYMBOL
spate
COMPARATOR
FIXWD
DIVIDER
DECODER
Semen
REFERENCE
ae
ieee
én
TEST
LOGIC
AND
OUTPUT
VOLTEGE
AND
SYNC
SELECTOR
SWITCH
2-2