JVC XV-D721BK - Page 27

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XV-D721BK
XV-D723GD
MN67705EA(3/3)
O
O
O
O
O
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
Pin No. Symbol I/O
DSL offset balance (FEP)
Focus drive
Tracking drive
Traverse drive A aspect
Traverse drive B aspect
Power supply for digital cirucuit
Off-track error signal (FEP)
Track crossing signal 1 (FEP)
Track crossing signal 2 (FEP)
Binary making data slice signal (FEP)
FG signal input (spindle motor driver)
Connects with DVSS
Connects with DVSS
Reset L : Reset
VCO reference current 1( for SYSCLK)
Ground for digital circuit)
VCO control voltage 1 (for SYSCLK)
33.8MHz system clock input
Ground for digital circuit
Spindle motor drive
CD/DVD control signal (FEP) CD : H DVD : L
Tracking ON (FEP)
Function
FS(AD2)
TS(AD1)
AVSS
AVDD
FBAL(DA1)
FC(DA2)
BOOST(DA3)
TBAL(DA4)
FODRV(DA5)
TRDRV(DA6)
TRSDRVA(DA7)
TRSDRVB(DA8)
DVDD
OFTR
TKCRS1
TKCRS2
DSLO
FG
MINTEST
TEST
XRESET
IREF1
DVSS
VCOF1
SYSCLK
DVSS
EC(PWM3A)
ECR(PWM3B)
N.C.(PWM3A)
N.C.(PWM2B)
N.C.(PWM1A)
CDDVD
N.C.(PWM0A)
N.C.(PWM0B)
FEPNTRON
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
FS (FEP)
TS (FEP)
Ground for analog cirucuit
Power supply for analog circuit
Focus balance(FEP)
Cutting off frequency (FEP)
Amount of boost (FEP)
I
I
O
O
O
Clamp
1.25V
6dB
75
driver
1.5
1.5
5k 5k
5k5k
100k
6dB
75
driver
6dB
75
driver
Reference
&
Standby
logic
Camp
1.25V
Bias
2.0V
2
5
6
1
12
11
10
9
8
347
Y-INPUT
STANDBY
C-INPUT
Y-OUTPUT
Y-SAG
CVBS
-OUTPUT
CVBS-SAG
C-OUTPUT
GND
VCC
1
2
3
4
5
6
12
11
10
9
8
7
VCC
Y-INPUT
GND
GND
STANDBY
C-INPUT
Y-OUTPUT
Y- S A G
CVBS-OUTPUT
CVBS-SAG
C-OUTPUT
GND
TK15400(IC701):Video AMP.
1.Pin layout 2.Block diagram