JVC XV-N40BK - Page 23

XV-N40BK,XV-N44SL
(No.A0040)1-23
SECTION 4
Description of major ICs
4.1 74LCX373APW-X (IC512,IC513) : Octal D-type latch
•Pin layout
• Pin function
• Truth table
H = HIGH Voltage level
L = LOW Voltage level
Z = High impedance
X = Immaterial
Q0 = Previous Q0 before HIGH to LOW transition of latch enable
• Block diagram
Symbol Description
D0~D7 Data inputs
LE Latch enable input
OE
Output enable input
Q0~Q7 3-State latch outputs
1OE
2Q0
3D0
4D1
5Q1
6Q2
7
20
19
18
17
16
15
14D2
VCC
Q7
D7
D6
Q6
Q5
D5
(TOP VIEW)
8D3
9Q3
10GND
13
12
11
D4
Q4
LE
INPUTS OUTPUT
LE OE
Dn Qn
XHXZ
HLLL
HLHH
LLXQ0
Q
L
D
D0
3
2
Q0
11
1
LE
OE
Q
L
D
D1
4
5
Q1
Q
L
D
D2
7
6
Q2
Q
L
D
D3
8
9
Q3
Q
L
D
D4
13
12
Q4
Q
L
D
D5
14
15
Q5
Q
L
D
D6
17
16
Q6
Q
L
D
D7
18
19
Q7