......
Sixteen such DMA operations will occur
in
succession, until
the
FIFO is filled. At this point,
~he
sampling clock will be enabled
(free
running'
mode). Nothing will happen until the first sampling
clock tick occurs, which signifies that a sound sample is requested
at the
Signal Channel Data
in
the Ghannel. The CGP simply pops the
first
FIFO'd sample onto the DAC BUS, updates the CSW (now
indicating
that
the FIFO is not full), and proceeds to the next·
channel. On the next poll, the CGP will perform another DMA
operation to keep the
FIFO full.
Another function concerns when the DMA address matches the
micro-programmed DMA
LAST ADDRESS. This will generate a
vectored interrupt of the main
CPU, and invert the TOGGLE BIT,
which points to one of 2 sets of parameters which the CGP
processes.
In
this way, the DMA operation is not stopped at the end
of each waveform, the main
CPU has one full waveform to update the
other parameter set
in
the
CG
P local memory.
If
an
interrupt has been generated by one channel, and another
channel also reaches the End-of-Waveform before the first interrupt
has been serviced; a bit is set
in
the CSW and the interrupt
is
issued
on
the next DMA cycle
in
which
an
interrupt is not pending.
Finally, when the amplitude of the signal has been ramped
down to inaudible, the channel may be de-allocated by writing a zero
to
a bit
in
the Channel Enable Word.
Now, we can look at the
CGP State Diagram (figure 3.7) to
trace the cycle by cycle operation of the CGP.
On
RESET!, the CGP
is
initialized to state
0,
then it unconditionally jumps into state
F,
which increments the Channel Count (CHCNT), which will
be
stable'
before the end of state
F.
In
addition, the CPU may want
to
access
the Group Processor,
so
that if CPGPRQ!
is
active, State F
is
when
the CPU-Group Processor communication occurs
(CPGPIP). When the
access
is
complete, or if
no
access occurs, the CGP reads the CSW
in
State
D.
The status should be latched and stable by the end of this
clock cycle. The appropriate bit of the
CEW which determines the
Channel Enable (CHEN) should also be present at the PAL input,
and·
determines whether the CSW should be ignored (State
F)
or looked at
(State 3). '
Kurzwell
250
Service Manual, Chapter 3
3 - 1 9
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