Kurzweil K250 - Page 53

)
Figure 3.6 - CGP BLOCK DIAGRAM
CGPSEL
SFAS
--
CGWR
LDTACK
r
(CP SOUND)
TO CPU
BOARD
CGAS
CHSEL / 4
SOUND FILE
CGP ENGINE
MEMORV
CGSFIP
CHRDRQ
SFACK
16 CHANNEL
--
-
LDDAC
2 PORT
DMA CONTROLLER
(access from CPU
or CGP)
I
SfADDR
(SOUNDFILE
1
ADDRESS BUS) I
buffer
I
,24
,
16
I
1
ADDR
( MA I N ADD R ESS BUS)
Sf DATA
1 (SOUNDFI LE DATA BUS)
I
buffer
J
1
DATA
(MAIN DATA BUS)
ANASEL
Kurzwell 250 Service Manual, Chapter 3
3 - 2 1
CDB /12
,-
L6
,
" 16
,
TO CHANNEL
BOARD