Lattice Semiconductor ECP5 User Manual

7
ECP5 PCI Express Board User’s Guide
On-Board Clock Capabilities (See Appendix B, "Clock Generation" and "LPDDR3" sheets)
The ECP5 PCI Express Board allows for several clock source options. Some of these options are controlled via the
ispClock5304 programmable clock manager device. The clock manager will be supplied by a 54 MHz clock on-
board oscillator or an external clock source. The LPDDR3 clock will be supplied directly from a 100 MHz on board
oscillator.
Table 2. Clock Sources
SERDES
The ECP5 based SERDES FPGA is utilized on the board for several purposes. The SERDES block is provisioned
to provide a single, full-duplex PCI Express channel. The high-speed signals are connected to the PCI Express
edge connection.
Clock Destination Clock Sources Control Switch Setting
ECP5 ball AD32 site
LRC_GPLL0T_IN
54 MHz On board Oscillator X1 SW7[7]=0, ispClock5304 PLL can be used
by setting SW7[8]=1
External Clock J4 SW7[7]=1, ispClock5304 PLL can be used
by setting SW7[8]=1
ECP5 ball A17 site
ULC_GPLL0T_IN
54 MHz On board Oscillator X1 SW7[7]=0, ispClock5304 PLL can be used
by setting SW7[8]=1
External Clock J4 SW7[7]=1, ispClock5304 PLL can be used
by setting SW7[8]=1
ECP5 ball C5/D5 site ULC 100 MHz On board Oscillator U32
Connector CN1 (Left) 54 MHz On board Oscillator X1 ispClock5304 PLL can be used by setting
SW7[8]=1
Connector CN2 (Right) 54 MHz On board Oscillator X1 ispClock5304 PLL can be used by setting
SW7[8]=1

Lattice Semiconductor ECP5 Specifications

General

Brand	Lattice Semiconductor
Model	ECP5
Category	Recording Equipment
Language	English