LG 32LN57 Series - Page 67

4. Tuner/CI Block Diagram
LGE 2122
TDSQ-
G501D
[RESET] 2 AG24 [ADIN6_SRV]
AF19[OPCTRL1]
AJ19 [OPCTRL0]
[SLC] 3
[SDA] 4
[+3.3V_TUNER] 5
[+.1.8V_TUNER] 7
[T/C_DIF[P]] 10
[T/C_DIF[N]] 11
[ERROR] 16
[SYNC] 17
[VALID] 18
[MCLK] 19
R29 [DEMOD_TSSYNC]
P27 [DEMOD_TSVAL]
P30 [DEMOD_TSCLK]
[D0-7] 20-27
[+1.23V_S2_DEMOD] 30
[S2_RESET] 31 AM18 [ADIN7_SRV]
[+3.3V_S2_DEMOD] 32
LNB
IC6900
A8303SESTR-TB
10 [TONECTRL]
2 [LNB]
7 [SCL]
8 [SDA]
[S2_F22_OUTPUT] 33
[LNB] 36
[S2_SCL] 34
[S2_SDA] 35
AP6 [SCL3]
AR6 [SDA3]
AM27 [ADCINP_DEMOD]
AN27 [ADCINN_DEMOD]
/TU_RESET1
IC2_SCL6
IC2_SDA6
FE_DEMOD1_TS_SYNC
FE_DEMOD1_TS_VAL
FE_DEMOD1_TS_CLK
FE_DEMOD1_TS_DATA [0-7]
+1.23V_D_Demod
/S2_RESET
LNB_TX
I2C_SCL4
I2C_SDA4
22 Ω
LNB_OUT
+3.3V_NORMAL
3.3K Ω
+1.8_TU
+3.3V_TU
+3.3V_D_Demod
IF_P
IF_N
TUNER_SIF(for T2/C/S)
TU_CVBS(for
T2/C/S)
IF_AGC
ADCINP_DEMOD
ADCINN_DEMOD
33 Ω33Ω
Attenuator
47 Ω
MT5398_TS_OUT[0-7] CI_MDI[0-7]
CI Slot
47 Ω
MT5398_TS_IN[0-7] CI_TS_DATA[0-7]
/PCM_WE
/PCM_OE
/PCM_IRQA
/PCM_A_REG
PCM_INPACK
/PCM_WAIT
PCM_RST
CI_DATA[0-7] CI_A_DATA[0-7]
CI_ADDR[0-14] CI_A_ADDR[0-14]
/PCM_IORD
/PCM_IOWR
/PCM_CE2
/PCM_CE1
CI_VS1
/CI_CD1
/CI_CD2
CI 5V
Power detect
PCM_5V_CTL
+5V_CI_ON
CI_TS_SYNC
CI_TS_VAL
CI_TS_CLK
MTK5398_TS_SYNC
MTK5398_TS_VAL
MTK5398_TS_CLK
[DEMOD_TSDATA0-7]
[GPIO18-25] TS_IN[0-7]
[GPIO34-41] TS_OUT[0-7]
CI_DET1
L33[SPI_CLK]
CI_DET2
L30[SPI_CLK1]
VS1M27[PVR_TS_VAL]
M31[CI_TSCLK] CARD_EN1
CARD_EN2
10K Ω
N34[SPI_DATA]
N35[SPI_CLE]
IOWD
IORD
[GPIO0-14]
[GPIO26-33]
ADDR[0-14]
DAT[0-7]
T34[DEMOD_RST]
P34[PVR_TSDATA1]
N36[CI_INT]
P33[PVR_TSDATA0]
R36[CI_TSVAL]
R37[CI_TSSYNC]
R33[PVR_TSSYNC]
R3[PVR_TSCLK]
R35[CI_TSDATA0]
TS_OUT_CLK
TS_OUT_VAL
TS_OUT_SYNC
CI_RESET
CI_WAIT
INPACK
REG
/IRQA
O_EN
WR_EN
VCC
F28[TCON12]
+5V_CI_ON +3.3V_NORMAL
47K Ω
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Only for training and service purposes
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