LG 32LV3300 - Block Diagram

- 14 -
LGE Internal Use OnlyCopyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BLOCK DIAGRAM
RG
B P
C
S
PDIF
Component
H/ P OUT
HDMI(DV
I)
Half
H
al
f
NIM
NIM
(
C
A
N)
(
CAN)
P
C/ DVI Au
d
i In
RS-
23
2
C
IF +/ -
TU_
C
VBS
SIF
L/ R
S7M- R
MAX3232
SERI
AL FLASH
MXIC (8M bit)
M
5
M2
I
X- tal
24.69M
LVDS
(HD o
r FHD or FHD 100/ 120Hz
)
A. AMP
NTP7100
USB2
.
0
DP/D
M
S
P
K L/ R
X
-
tal
1
2
M
FFC(51P) : FHD 50/ 60Hz
FHD 100/120Hz
I2S
SPDIF
H/
P L/ R
L/ R
CVBS, Y/Pb
/Pr, L/
R
RGB/H/V
RS23
2C
Rear
TMDS
DDR2 Add .
DDR2 Data
SPI
M
IC
O
M
UP
D
7
8F
0
5
14A
GA
-
G
A
M- A
X
MICOM SDA
MICOM SCL
A
V
Side
NAND Flas
h
(2
G
bi
t
)
H
Y
27UF082G2B- TP
C
B
PCM_A
[0
:7
]
DDR
3
2
5
6
M
H
ynic
H
5
TQ1G63BFR
FFC(31P) : HD 50/ 60Hz
TMDS
HDMI
CVBS, L/
R
D
D
R3 256M
H
y
n
i
c
H5
T
Q1G
6
3
B
FR
DD
R3 256M
H
ynic
H5T
Q1G
63B
F
R
CONTROL
IR & LED /
S
O
FT
T
O
UCH
NEC_
EEPROM
_SCL/SDA
LED_
R/ BUZZ
KEY1
KEY2
IR
LED
_
B/ LG L
OGO
SO
FT TOUCH
_SCL/SD
A
M24M01- HRMN6TP
1Mbi
t
HDCP EEPROM
CA
T24W
C0
8
W-
T
I2C
MICOM EEPROM
M24C16- WMN6T
16Kbit
H
DMI
E
EPR
OM
AT2
4
C
0
2
BN- SH- T
RGB
E
EPR
O
M
AT24C02BN-
SH
-
T
I2C
I2C
HDMI
E
EPR
O
M
AT
2
4
C
02BN
-
S
H
-
T
HDMI EEPROM
AT24C
0
2
BN
-
S
H
-
T
I2C
LED D/ L pin
SCL/ SDA
SERIAL FL
A
SH
F
o
r External U
RSA
5
SPI
A. AMP
NTP
7
1
00
WOOFER L/ R
I2S
L/ R
FPC(41P) : FHD 100/ 120Hz